Beyond Software: The Virtual-Machine Supply System

It’s no secret that EDA and IP companies have had to expand their coverage into the larger system market, thanks to changes in the semiconductor supply chain. Around 2000, the industry was very fragmented. Mobile-chip and IP vendors worked with handset makers, who then partnered with operating-system (OS) suppliers and finally network operators. The next 12 years resulted in various combinations of subsystem integration.

To aid that integration, EDA and IP companies such as Cadence, Mentor, and Synopsys had to provide not only hardware but also software (drivers and firmware) to their customers. Now, semiconductor companies face additional challenges as the manufacturing and supply chain have evolved to meet the needs of a consumer-driven global market.

With ever-decreasing time-to-market cycles for electronic products, companies in the chip, board, and package markets must expand their systems viewpoint beyond design to include the manufacturing and even the distribution process. “Manufacturing,” in this sense, refers to more than just the design-focused implementation techniques like design-for-manufacturing (DFM) and design-for-yield (DFY). It includes the larger manufacturing and supply-chain issues, as well.

Perhaps not surprisingly, this expanded systems viewpoint is often described in the vernacular context of a technical system. “We call it supply-chain operating system,” explains Geoff Annesley, CTO at Serus, a provider of manufacturing and supply-chain visibility solutions. “You can think of your supply chain as a collection of factories, warehouses, and processes all distributed around the world. It is like one giant machine to which you send signals and collect data to understand, control, and measure it. It is like a virtual machine (VM) that requires an OS to handle it.”

From the perspective of the multi-tiered supply chain, circuit creation and layout is but one dimension of this larger design effort. Another dimension is the manufacturing of that design. Building chips or boards requires planning, coordination, and management across multiple factories and suppliers.

Just as design intellectual property (IP) cores are needed to build complex system-on-chips (SoCs), manufacturing IP is needed to build and manage the production process. “That’s why semiconductor companies like Qualcomm Atheros, nVidia, and others work with us to manage all of their internal manufacturing foundry IP,” said Annesley.

But managing the global manufacturing process is only part of the challenge. Data must be collected and analyzed to ensure that design results in the expected end product meet specification. For example, did the supplier use the right test program version? Did they set up the machine correctly? A virtual supply-chain OS is needed to measure actuals and correlate them with the specifications across multiple factories, test cycle times, and more.

But the analogy of a virtual machine (VM) being run by an OS doesn’t fit all scenarios. “The virtual-machine analogy fits in so well that a VM ‘appears’ to be running as part of the same system. But in fact, the VM and the host OS are entirely different systems from an application perspective,” notes Brian Haacke, Industry Sales Director for High Tech at Dassault Systemes. “What I don’t like about the analogy is that the OS and VM are sharing the same hardware. I would consider more degrees of separation for companies that do not have a supply-chain OS strategy. To me (in today’s world), it is more like having a standalone PC and a standalone MAC passing data back and forth over a USB key.”

Regardless of discrepancies in the VM and OS analogy, the need for a supply-chain OS or its equivalent is strong. “The history of information flow from design through to fabrication and assembly has been very poor, considering the technical abilities that we have today,” says Michael Ford, marketing development manager of Mentor Graphics’ Valor Division.

On the design side, the problem comes partially from the varied and antiquated way in which design information is communicated. But changing the format is difficult. “Some justify these older formats by saying that they have IP (security) issues with sending the whole information. Others say that there is no ‘standard.’ And the majority is probably not aware that there is another way. As a result, detail in the data is lost, significant re-engineering is required, and many ‘trial and error’ revisions are required,” says Ford.

BOM problems
Another way of looking at the larger design-manufacturing supply-chain challenge is from the perspective of the bill of materials (BOM). A BOM is a list of all materials, components, parts, and subsystems as well as the quantities of each that are required to manufacture an end product. BOMs are commonplace in the mechanical space and in electronic printed-circuit-board (PCB) design. Now, they have started to appear in the semiconductor space.

The BOM perspective is helpful but not without problems. Often, board-level designs are laid out in such a way that several product revisions can easily be derived from the original. This results in fragmentation in BOM planning and management, explains Ford. The BOM information is incorporated into various product models contained within the business supply-chain tools, such as Enterprise Resource Planning (ERP), so that parts may be ordered. Unfortunately, most of today’s ERP systems “corrupt” the reference data by treating it as no more than a comment. After all, they are designed to work only on part number and quantity.

“In the semiconductor space, the design data is a mixture of both design data and IP,” notes Michael Munsey, Director for Dassault Systemes’ Product Management ENOVIA Semiconductor Solutions. “As you start to assemble your chip, you begin to form the notion of an IP BOM. As the design becomes finished, you start worrying about the manufacturing issues and creating a manufacturing-level BOM. That entire process has to be managed.”

Managing the manufacturing process is the domain of computerized manufacturing execution systems (MESs). MESs handle and track the execution of the products being built. In doing so, they provide visibility into how the current conditions on the plant floor can be optimized to improve production.

An MES is different from the other common supply-chain-based processes: product lifecycle management (PLM) and enterprise resource planning (ERP). PLM focuses on design and product development, while ERP manages the commercial business of manufacturing. “Neither the design system, ERP, PLM, nor MESs can effectively master the data today,” remarks Ford.

Scaling challenges
None of these processes are well integrated with one another. The MES is typically outside the scope of what would be measured in a PLM system. Furthermore, each of these processes needs to be managed across not just one but many manufacturers. “It is this scaling factor that has become the challenge for semiconductor companies (e.g., how to manage this across a whole project lifecycle),” explains Munsey.

Scaling of a different sort also is shaking up the traditional semiconductor supply chain from the inside. For many years, engineers and consumers have benefited from the direct scaling of digital-silicon CMOS designs. But the observation that defines this scaling, called Moore’s Law, is beginning to fatigue as process geometries approach atom-sized dimensions. Many designers and manufacturers are turning to stacked die as a cost-effective alternative to traditional digital scaling. These are technology-scaling issues (i.e., directly connecting one die to another within the same package) in contrast to supply-chain scaling issues. Yet the two are related.

“As we move from traditional single-die chips to the era of 2.5-dimensional (2.5D) stacked dies, everything changes,” cautions Naveed Sherwani, President and CEO at Open Silicon, a chip design-services company. “With a 2.5D package, naked dies have to be tested, placed on interposers, and then connected into a single package. The industry has never tested or sold anything like this before. It will disrupt the normal supply chain and its well-understood chain of command.”

In today’s semiconductor supply chain, wafer companies make wafers, packaging companies do packing, and testers do tests. “But with 2.5D (stacked dies), this structure will be dramatically changed due to the interposer,” explains Sherwani. “Who will actually make the interposer? With stacked die, designers are making smaller chips on higher (less expensive) geometry nodes. You don’t need that much wafer, which means that wafer foundries may change. But the interposer and the whole package are currently in the domain of the wafer fabs. Conversely, the package companies see the interposer as nothing but another packaging technology being done at the chip level, which belongs to them.” These different perspectives and shifting responsibilities will result in disruptions between critical supply chains—namely, wafer foundries, package manufacturers, and test providers.

Many changes lie ahead for the semiconductor industry, ranging from ever-increasing SoC design complexities to the manufacturing difficulties of lower geometries and the alternate techniques of stacked die. Add to these non-trivial technical issues the dynamics of managing the global factories and supply chains, and the problems may seem insurmountable. But they are not, as proven by continued growth of the semiconductor market. Engineers are smart. Given the right insight and tools, they have overcome amazing challenges. “The key is for companies to have visibility into their supply-chain data while making informed decisions based on the intelligent correlation of requirements, design, simulation, test results, and yield data,” notes
Haacke.

It has taken many years for the semiconductor, EDA, and IP industries to integrate software into their chip hardware. The next step is to expand their view of the system to also include global manufacturing and supply-chain issues.