The Week In Review: Design


Tools Aldec released the latest version of its Riviera-PRO verification platform, adding QEMU Bridge to enable hardware/software co-simulation of designs intended to run on SoC FPGAs. Other features include improved performance when using code containing many inline randomized calls and up to 29% faster simulation speed of UVM. Pulsic added new features to its Unity Bus Planner for planning... » read more

The Week In Review: Manufacturing


Packaging and test A*STAR’s Institute of Microelectronics (IME) has formed a fan-out wafer-level packaging consortium comprising of OSATs, materials vendors, equipment suppliers and others. The group is called the FOWLP Development Line Consortium. As part of the announcement, Singapore’s IME has established a development line to accelerate the development of fan-out. Located in IME’s... » read more

The Week In Review: Design


Tools Cadence unveiled a new equivalence checking tool which features a massively parallel architecture capable of scaling to 100s of CPUs and adaptive proof technology that analyzes each partition and determines the optimal formal algorithm. According to the company, the Conformal Smart Logic Equivalence Checker provides an average of 4X runtime improvement with the same resources over the pr... » read more

Hybrid Emulation


Semiconductor Engineering sat down to discuss the growing usage of hybrid verification approaches with Frank Schirrmeister, senior group director of product management & marketing for [getentity id="22032" e_name="Cadence"]; Russ Klein, program director for pre-silicon debug products at [getentity id="22017" e_name="Mentor, a Siemens Business"]; [getperson id="11027" comment="Phil Moorby"],... » read more

Hybrid Emulation


Semiconductor Engineering sat down to discuss the growing usage of hybrid verification approaches with Frank Schirrmeister, senior group director of product management & marketing for [getentity id="22032" e_name="Cadence"]; Russ Klein, program director for pre-silicon debug products at [getentity id="22017" e_name="Mentor, a Siemens Business"]; [getperson id="11027" comment="Phil Moorby"],... » read more

Monday At DAC


The 54th DAC got started today in a very steamy Austin. While we may be a maturing industry, there is certainly no indications that the people within the industry have given up or intend to take it easy. The event really got started late Sunday when Laurie Balch, chief analyst for Gary Smith EDA, delivered her message. She said that the focus is becoming the verticals. "This change in focus is ... » read more

The Week In Review: Design


Name Changes Arteris changed its name to ArterisIP. The company said the name change better reflects what the company does, which is provide IP for SoC communication on-die and between die. Mentor Graphics also modified its name, following last week's announcement that the acquisition by Siemens has been completed. The company is now officially called Mentor, A Siemens Business. It also ... » read more

CEO Outlook: Chip Design 2017


After two consecutive flat to slightly down years, the semiconductor industry is poised for growth in 2017. Cowan this month predicted 4.7% growth in semiconductor sales in 2017, while World Semiconductor Trade Statistics (WSTS) put that figure at 3.3%. And last month, International Business Strategies (IBS) pegged the number at 4.6%, according to statistics compiled by the Global Semiconduc... » read more

Making 2.5D, Fan-Outs Cheaper


Now that it has been shown to work, the race is on to make advanced [getkc id="27" kc_name="packaging"] more affordable. While device scaling could continue for another decade or more, the number of companies that can afford to develop SoCs at the leading edge will continue to decline. The question now being addressed is what can supplant it, supplement it, or redefine it. At the center o... » read more

The Week In Review: Design


Numbers EDA and IP sales increased 5.6% in Q2 to $2.013 billion, up from $1.907 billion in the same period in 2015, according to the most recent Electronic System Design Alliance numbers. Asia/Pacific revenue increased 10.9% to $608.1 million; Japan increased 15.7% to $211.4 million. The Americas increased 4.4% to $908.4 million. IP Cadence launched the latest generation of its Xtensa ... » read more

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