The Week In Review: Design

Name changes; machine learning in EDA; neural network interconnect; IoT IP bundle; chip-to-chip interface IP; Imagination loses Apple deal.


Name Changes

Arteris changed its name to ArterisIP. The company said the name change better reflects what the company does, which is provide IP for SoC communication on-die and between die.

Mentor Graphics also modified its name, following last week’s announcement that the acquisition by Siemens has been completed. The company is now officially called Mentor, A Siemens Business. It also has licensed the name Mentor Graphics, A Siemens Business.


Solido Design Automation announced an interesting direction for the company after the experience they have gained over the past twelve years with machine learning. In addition to announcing release of the Machine Learning (ML) Characterization Suite, a product that uses machine learning to reduce standard cell, memory, and I/O characterization time, the company also launched Machine Learning (ML) Labs. This initiative makes its machine learning technologies and expertise available to collaboratively work with semiconductor companies to develop new ML-based EDA products.

Cadence expanded its Virtuoso Advanced-Node Platform to support advanced 7nm designs. The tool provides a variety of layout capabilities, including multi-pattern color awareness, FinFET grids, and module generator device arrays, as well as variation analysis utilizing Monte Carlo analysis across corners. MediaTek used the tool in a recent tapeout.


ArterisIP launched the latest generation of its distributed heterogeneous cache coherent interconnect IP, Ncore 2.0. The IP targets neural network SoCs for ADAS and autonomous driving systems, allowing integration of custom processing elements using embedded low latency proxy caches. In neural networks, low latency proxy caches offer a more hardware- and software-efficient way of communicating between all the different elements, according to the company. A resilience package that provides functional safety features for ISO 26262 ASIL D compliance is also available.

ARM bundled several system-level IP for embedded and IoT applications into a single design kit aimed to complement the Cortex-M processor family. The kit includes CMSDK, AHB Flash Cache, CoreLink SIE-200 system IP and the CoreLink SSE-200 subsystem.

Open-Silicon debuted its eighth-generation Interlaken chip-to-chip interface IP core, supporting up to 1.2 Tbps high-bandwidth performance and up to 56 Gbps SerDes rates with Forward Error Correction (FEC). Other features include allowing a single instance of the core to have multiple configurations selected at power-up and multiple user-data interface options.

Automotive & Safety

Mentor uncorked a new sensor fusion platform for autonomous vehicles. The platform directly transmits unfiltered information from all system sensors, including radar, LIDAR, and vision, to a central processing unit, where raw sensor data is fused in real time at all levels. It uses a Xilinx Zynq UltraScale+ MPSoC device in the first generation, and accommodates SoCs and safety controllers based on either X86- or ARM-based architectures.

Mentor’s Embedded Nucleus SafetyCert real time operating system now supports the ARM Cortex-M4 processor. The RTOS’ networking has been extended to include a certifiable IPv4 TCP/IP stack, and connectivity extended to include SPI and I2C.


Apple notified Imagination that it will stop using Imagination’s IP in its new products in 15 months to two years, and as such will not be eligible for royalty payments under the current license and royalty agreement. Apple, Imagination’s largest customer, says it has been working on a separate, independent GPU. Imagination’s stock price fell more than 60% over last weekend to its lowest point in seven years, wiping out gains made in the past year as the company restructured.

Sunplus Technology signed a multi-year license agreement for NetSpeed’s Orion on-chip network IP, which the company will use in future generations of its automotive infotainment SoCs. Sunplus cited functional safety features that can be configured to achieve ASIL-B through ASIL-D level.

Juniper Networks used Cadence’s power integrity solution in a successful tapeout of its largest ever switch-chip FinFET design.


MIPI CSI-2SM v2.0, the latest version of the MIPI Camera Serial Interface (CSI-2) specification, was released. Updates to the specification focus on imaging and vision for an expanded range of applications  such as IoT and automotive, and include RAW-16 and RAW-20 color depth, expanded virtual channels from 4 to 32, and Latency Reduction and Transport Efficiency (LRTE) for image sensor aggregation.

The prpl Foundation and EEMBC will collaborate on creating an industry-standard hypervisor benchmark, focused on assessing the performance of new lightweight embedded hypervisors paired with SoCs with hardware support for virtualization.


Registration opened for DAC’s “I Love DAC” campaign, sponsored by ClioSoft, OneSpin and Truechip. The program provides free entry to the exhibits on Monday, Tuesday and Wednesday (June 18 – 22, 2017) plus entry into the four keynotes and the DAC Pavilion, which includes SKYTalks, Fireside CEO Chats, three teardowns and industry panel discussions.

PLDA will host the first PLDA Design Days on May 18, 2017 in Shanghai, China. The event will be entirely focused on PCIe 4.0 connectivity and will feature a panel of speakers representing all of the critical functions in chip design including PHY, Verification IP, ASIC design, and controllers including NVMe. The event is free to attend.

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