The Week In Review: Design

Equivalence checking; multi-FPGA prototyping; DFM; CCIX collaboration; memory.


Cadence unveiled a new equivalence checking tool which features a massively parallel architecture capable of scaling to 100s of CPUs and adaptive proof technology that analyzes each partition and determines the optimal formal algorithm. According to the company, the Conformal Smart Logic Equivalence Checker provides an average of 4X runtime improvement with the same resources over the previous generation.

Aldec launched the latest version of its HES-DVM verification environment, adding a new prototyping mode with design partitioning and partition interconnection tools to aid multi-FPGA prototyping.

Cadence launched a real-time, in-design DFM tool. Allegro PCB DesignTrue DFM provides continuous in-design feedback to verify spacing between copper features such as traces, pins, vias relative to the board outline and other copper features in real time, independent of electrical and net-based rules.

Xilinx, Arm, Cadence, and TSMC are collaborating on a Cache Coherent Interconnect for Accelerators (CCIX) test chip. The test chip will include Arm DynamIQ technology, CMN-600 coherent on-chip bus and foundation IP, Cadence key I/O and memory subsystems including CCIX IP plus verification and implementation tools, and connect to Xilinx 16nm Virtex UltraScale+ FPGAs. The chip will be implemented on TSMC’s 7nm FinFET process and is expected to tape-out in early Q1 2018.

Arastu Systems announced R-DIMM and LR-DIMM support for its DDR4 Controller. The controller is compliant with the latest JEDEC DDR4, RCD standards and also supports Non-Volatile DIMM (NVDIMM) based products.

Mobiveil and Crossbar are working together on a new ReRAM-based design from Mobiveil’s complete PCIe-to-NVMe set of SSD IP with Crossbar’s ReRAM enabling six-million 512B IOPS below 10us latency, with the goal of speeding up access to frequently requested information in large data centers.

UltraSoC will open a second UK location following the completion of a $6.4m funding round. The company provides embedded analytics IP.

QuickLogic’s eFPGA technology is now available on SMIC’s 40nm Low Leakage process.

TSMC Updates
Synopsys announced foundation IP, including logic libraries and embedded memories, for TSMC’s 40nm ultra-low power (ULP) eFlash and 40nm low-power (LP) eFlash processes.

Mentor’s Calibre physical verification platform and Analog FastSPICE have been certified for TSMC’s 12nm FinFET Compact and the latest 7nm FinFET Plus processes. They, along with the Xpedition packaging tool, were also updated to improve support for TSMC’s InFO integrated fan-out advanced packaging and CoWoS chip-on-wafer-on-substrate packaging technologies.

Synopsys’ IC Complier II place-and-route tool was certified for TSMC’s 7nm FinFET Plus process and validated on multiple high-performance production designs. It was also certified for the latest TSMC 12nm FinFET process and supports multi-die integration using CoWoS technology.

Cadence digital, signoff and custom/analog tools have been certified for TSMC’s 7nm FinFET Plus process and the 12nm FinFET Compact process. The Cadence library characterization flow has been updated to support 7nm FinFET Plus and the 7nm process. Additionally, the company completed its design flow for TSMC’s InFO packaging technology and enhanced its CoWoS reference flow.

eSilicon taped out a deep learning ASIC incorporating custom pseudo two-port memories designed by eSilicon, TSMC’s Chip on Wafer on Substrate (CoWoS) technology, 28G SerDes, and four second-generation high-bandwidth memory stacks (HBM2)

Open-Silicon completed silicon validation of its HBM2 IP subsystem in TSMC’s 16nm FinFET technology in combination with CoWoS 2.5D technology. The subsystem includes an HBM2 controller, PHY and interposer I/O, and completes the critical components needed for integration of HBM2 memory into ASIC system-in-package designs.

Alango’s Voice Enhancement Package has been optimized for Synopsys’ ARC Data Fusion IP Subsystem. The package offers multi-microphone beamforming array and echo cancellation technologies for speech recognition.

Renesas licensed ArterisIP’s FlexNoC interconnect IP. Renesas is a longtime customer of the company.

A new book, Formal System Verification, has been released by Springer. Edited by Dr. Rolf Drechsler of the University of Bremen, the book delves into the formal verification of hardware and software and a variety of applications. A chapter focusing on an industry perspective of the technology was supplied by Raik Brinkmann and Dave Kelf of OneSpin.

Ansys announced a guide that outlines the various methodologies to simulate, debug and optimize electronic chips for automotive applications on TSMC’s 16-nanometer FinFET Compact Technology (16FFC) process and Automotive Design Enablement Platform (ADEP).

John Wall, corporate vice president of finance and corporate controller of Cadence, has been appointed senior vice president and chief financial officer, effective October 1. Geoff Ribar, current CFO of Cadence, will remain with the company as a senior advisor until his previously announced retirement at the end of March 2018. Wall is a 20-year veteran of the company.

IR4 (Fourth Industrial Revolution): The Cognitive Era: Sept. 20, 6-8:30pm at San Jose State University, San Jose, CA. Jim Hogan will discuss cognitive science, how it brings together methods and discoveries from neuroscience, psychology, linguistics, philosophy and data/computer science, and how people, animals or computers think, act and learn.

ARC Processor Summit: Sept. 26 in Santa Clara, CA. Opening with a keynote by Jeff Bier of the Embedded Vision Alliance and BDTI on how AI and machine learning are transforming electronic products, the day features concurrent tracks dedicated to hardware, software, and embedded vision.

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