The Week In Review: Design

By Jesse Allen - 15 Sep, 2017 - Comments: 0

Tools Cadence unveiled a new equivalence checking tool which features a massively parallel architecture capable of scaling to 100s of CPUs and adaptive proof technology that analyzes each partition and determines the optimal formal algorithm. According to the company, the Conformal Smart Logic Equivalence Checker provides an average of 4X runtime improvement with the same resources over the pr... » read more

The Week In Review: Design

By Jesse Allen - 23 Jun, 2017 - Comments: 0

M&A Silvaco will acquire SoC Solutions, adding more IP experience to the company's portfolio. SoC Solutions, based in Atlanta, GA, focuses on pre-configured IP subsystems and IP targeting low power IoT and machine-to-machine communication. Terms of the deal were not disclosed, but the acquisition is expected to close soon. Imagination is putting the rest of the company up for sale after... » read more

The Week In Review: Design

By Jesse Allen - 21 Apr, 2017 - Comments: 0

Tools Mentor unveiled new formal-based technologies in the Questa Verification Solution. It offers formal-based RTL-to-RTL equivalence checking flows optimized for verification of manual low-power clock gating, bug fix and ECO validation, and ISO 26262 safety mechanism verification, which the company says which can reduce verification turnaround time by 10X. The app also offers expanded cloc... » read more

The Week In Review: Design

By Jesse Allen - 06 Jan, 2017 - Comments: 0

IP Arastu Systems uncorked a LPDDR3 DRAM Memory Controller. The controller is fully compliant with JEDEC standard JESD209-3C and supports various power down modes as well as multiple channels with a privilege to configure and manage each channel independently and parameterized data width. CSEM's Bluetooth Low Energy silicon RF IP has been validated as Bluetooth 5 compatible. RF test equip... » read more

The Week In Review: Design

By Jesse Allen - 12 Aug, 2016 - Comments: 0

IP Avery Design Systems released NVM Express over Fabrics 1.0 and NVM Express 1.2.1 extensions to its NVM-Xactor verification IP, enabling verification of both NVMe over PCIe and NVMe over Fabrics designs. Arastu Systems uncorked an optimized DDR3/4 DRAM Controller Core, which works with DFI 3.1 compatible PHY. The core supports all key DDR3/DDR4 features and additional features like Erro... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

tag: Arastu Systems

The Week In Review: Design

The Week In Review: Design

The Week In Review: Design

The Week In Review: Design

The Week In Review: Design