The Week In Review: Design

Formal equivalence checking; data fusion; cryogenic computing; memory makes for rosy outlook.



Mentor unveiled new formal-based technologies in the Questa Verification Solution. It offers formal-based RTL-to-RTL equivalence checking flows optimized for verification of manual low-power clock gating, bug fix and ECO validation, and ISO 26262 safety mechanism verification, which the company says which can reduce verification turnaround time by 10X. The app also offers expanded clock domain crossing capabilities for gate-level CDC analysis and allows for web browser and mobile views.


Synopsys updated its ARC Data Fusion IP Subsystem with a new suite of interface peripherals including pulse density modulation (PDM), I2S and I3C, as well as an audio processing software library to speed application software development. The subsystem is an integrated, pre-verified hardware and software IP product targeted at devices requiring minimal energy consumption.

Arastu Systems uncorked an Ethernet 10G Digital Switch IP soft core. The core can be configured to support 3 to 24 ports, where each port can act as 10M/100M/1G/2.5G/10G Ethernet with fully non-blocking switching. The IP offers complete support for Layer 2 protocol based switching for Unmanaged Switch and Managed Switch, partial support for Layer 3 protocol and optional support for Precision time protocol (PTP) 1588.

Dolphin Integration launched SpRAM (Single-port SRAM) optimized for low-power SoCs in TSMC 28 nm HPM technology. The SpRAM has a data retention mode, with a memory core lowered to 0.63 V. According to the company, the minimum voltage retention feature allows leakage to be divided by between 2 and 10 (depending on memory size) compared to other memory compilers in stand-by mode.

Faraday Technology released its V-by-One HS PHY & Controller IP on UMC 28HPCU process technology. The IPs, targeted at automotive infotaiment, surround view, and UHD display, are compliant with V-by-One HS standard version 1.4 and are able to support both TX and RX up to 4 Gbps data rate.

Truechip shipped early adopter versions of its JESD204B Comprehensive Verification IP (CVIP). According to Truechip, it provides block, SoC and System Level Verification across dynamic simulation, assertion based dynamic and formal verification, as well as support for hardware acceleration and emulation.


Rambus and Microsoft are teaming up to develop prototype systems that optimize memory performance in cryogenic temperatures. The technologies seek to improve energy efficiency for DRAM and logic operation at temperatures below −180 °C or −292.00 °F or 93.15 K, ideal for high-performance super computers and quantum computers. An additional focus is enabling high-speed SerDes links to operate efficiently in cryogenic and superconducting domains. The two companies plan to have an early prototype of cryogenic memory in a month.

Cambricon licensed Arteris’ FlexNoC interconnect IP for use as the backbone interconnect of its machine learning SoC. Cambricon targets all AI markets, and says its Cambricon-1A chip can handle 16 billion virtual neurons per second and has a peak capacity of two trillion synapses per second with less power consumption than a conventional GPU.

Rambus is partnering with Samsung Electronics for its recently launched 56G SerDes PHY to be developed on Samsung’s 10nm LPP (Low-Power Plus) process technology. The PHY provides PAM-4 and NRZ signaling with a scalable ADC-based architecture.

Market Research

Worldwide semiconductor revenue is forecast to total $386 billion in 2017, according to Gartner, an increase of 12.3% from 2016 driven primarily by increased memory prices. “While price increases for both DRAM and NAND flash memory are raising the outlook for the overall semiconductor market, it will also put pressure on margins for system vendors of smartphones, PCs and servers,” said Jon Erensen, research director at Gartner. “Component shortages, a rising bill of materials, and the prospect of having to counter by raising average selling prices (ASPs) will create a volatile market in 2017 and 2018.” Additional capacity in both DRAM and NAND flash is expected to result in a correction in 2019.

Meanwhile, DDR4 DRAM gained significant marketshare in 2016, representing 45% of total DRAM sales, according to IC Insights. DDR4 prices fell to nearly the same ASP as DDR3 DRAMs in 2016, and IC Insights expects DDR4 to become the dominant DRAM generation in 2017 with 58% marketshare.


Cadence’s Tensilica Vision P-Series DSPs passed the Khronos Group’s conformance tests for the OpenVX 1.1 specification for cross-platform acceleration of computer vision applications. Cadence also released an OpenVX 1.1 Application Programming Kit (APK) for Tensilica Vision DSPs.

Mentor’s Nucleus RTOS now supports the 64-bit ARMv8-A architecture. It also enables the ARMv8-A AArch32 (32-bit) execution mode, allowing users to run legacy 32-bit code on 64-bit SoCs. The initial reference implementation targets the NXP QorIQ LS2085A-RDB Reference Design Board.

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