中文 English

Week In Review: Design, Low Power


Tools, IP, chips Synopsys unveiled a new data-visibility and machine intelligence-guided design optimization solution. DesignDash is complementary to the company's DSO.ai AI-driven design-space-optimization tool and provides a real-time, unified, 360-degree view of all design activities. It uses deep analytics and machine learning to extract and reveal actionable understanding from large amoun... » read more

Week In Review: Design, Low Power


Tools & IP MIPS announced its first products based on the RISC-V ISA. The eVocore IP cores are designed to provide a flexible foundation for heterogeneous compute, supporting combinations of eVocore processors as well as other accelerators, with a Coherence Manager that maintains L2 cache and system-level coherency between all cores, main memory, and I/O devices. They target high-performan... » read more

Week In Review: Design, Low Power


Tools Synopsys introduced a new model for using its EDA tools on the cloud. Synopsys Cloud provides pay-as-you-go access to the company's cloud-optimized design and verification products, with pre-optimized infrastructure on Microsoft Azure to address higher levels of interdependencies in chip development. "As more design flows incorporate AI, requiring even more resources, the virtually unlim... » read more

Week In Review: Design, Low Power


Tools Imperas and Valtrix inked a multi-year distribution and support agreement that makes Imperas simulation technology and RISC-V reference models available pre-integrated within Valtrix STING for RISC-V processor verification. The combined solution covers the full RISC-V specification for user, privilege, and debug modes, including all ratified standard extensions, and the near ratified (st... » read more

Week In Review: Design, Low Power


Cadence will acquire NUMECA International, a provider of computational fluid dynamics (CFD), mesh generation, multi-physics simulation, and optimization solutions for industries including aerospace, automotive, industrial, and marine. “Next-generation products and systems require comprehensive multi-physics engineering solutions encompassing IP, semiconductors, IC packaging, modules, board... » read more

Week In Review: Auto, Security, Pervasive Computing


Arm's parent company, Japanese tech conglomerate Softbank, reportedly is considering a sale or IPO of its Arm subsidiary, which it purchased in 2016 for $32 billion in cash. Considering that Arm chips are in most smart phones, as well as an increasing number of computers and IoT and edge devices, this development is being closely followed by most of the tech world. Last week, Softbank directed ... » read more

Week In Review: Manufacturing, Test


Chipmakers Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. There are already signs that the foundries have pushed out their 3nm production schedules. So, expect 7nm and 5nm to become long-running nodes. At 3nm, Samsung and TSMC are going in different directions. Samsung is developing a gate-all-around (GAA) technology called nanosheet FETs. TSMC will e... » read more

Week In Review: Design, Low Power


Tools & IP Codasip unveiled its Codasip SweRV Core EH1 Support Package, which provides support for Western Digital's open source RISC-V-based core. The support package provides a comprehensive set of tools and components needed to design, implement, test, and write software for a SweRV Core-based SoC with support for leading EDA open and commercial flows. A free basic version is available ... » read more

Week In Review: Design, Low Power


MaxLinear will acquire Intel's Home Gateway Platform Division. MaxLinear, a provider of RF, analog, and mixed-signal ICs, will buy the Home Gateway Platform Division for an all-cash, asset transaction valued at $150 million. The division comprises Wi-Fi Access Points, Ethernet and Home Gateway SoC products deployed across operator and retail markets. The deal is expected to close in the third q... » read more

Week In Review: Design, Low Power


Accellera formed the Universal Verification Methodology Analog/Mixed-Signal Working Group (UVM-AMS WG), which will work to develop a standard that will provide a unified analog/mixed-signal verification methodology based on UVM to improve the verification of AMS integrated circuits and systems. “Our objective is to standardize a method to drive and monitor analog/mixed-signal nets within UVM,... » read more

← Older posts