The Week In Review: Design

Imagination up for sale; Silvaco buys SoC Solutions; update to AMBA CHI; RISC-V processor trace.


Silvaco will acquire SoC Solutions, adding more IP experience to the company’s portfolio. SoC Solutions, based in Atlanta, GA, focuses on pre-configured IP subsystems and IP targeting low power IoT and machine-to-machine communication. Terms of the deal were not disclosed, but the acquisition is expected to close soon.

Imagination is putting the rest of the company up for sale after receiving interest from several unnamed parties. In May, Imagination announced the MIPS and Ensigma groups were up for sale following a statement by Apple that it would no longer use Imagination’s GPU IP. According to the company, the sales are “progressing well and indicative proposals have been received for both businesses.”

UltraSoC developed processor trace support for products based on the open source RISC-V architecture. The specification for processor trace will be offered for adoption by the RISC-V Foundation. An implementation from the company will be available in Q42017.

Menta announced a validation board supporting TSMC’s 28nm High Performance Compact Plus (28HPC+) process. The board includes a test chip with an eFPGA IP core from Menta, and is supplied with all of the hardware and software required for validation of the complete eFPGA design flow.

Pro Design announced three new FPGA modules for its FPGA prototyping solution. Based on Xilinx Virtex and Intel Stratix, the boards are optimized for signal integrity and according to the company can reach a maximum point to point speed of up to 1 Gbps single ended over the standard FPGA IOs and up to 23 Gbps over the high-speed transceiver IOs with dedicated high-speed connectors.

ARM announced a major revision to the AMBA 5 Coherent Hub Interface (CHI) protocol, Issue B, with the aim of improving memory latency and data throughput on ARM’s latest generation of IP. Key features include cache stashing, far atomic operations, and RAS data protection signaling. The specification will be available for download later this year.

Cadence released its AMBA 5 CHI Issue B VIP. It includes all forms of CHI transactions, comprehensive checking, coverage models, and advance debug capabilities. It is complemented by tools for system-level data integrity for coherent and non-coherent interconnects and performance analysis capabilities to help optimize system performance.

Synopsys also uncorked VIP and a source code test suite for ARM AMBA 5 CHI Issue B. The VIP provides performance metrics for latency and throughput analysis, a configurable interconnect model, a reference verification platform and system-level checks for protocol, data integrity and cache coherency.

Rambus released a JEDEC-standard persistent memory register clock driver (NVRCD) for use with DDR4 non-volatile dual in-line memory modules (NVDIMM). According to the company, the NVRCD enables NVDIMMs to combine the performance of DRAM with the persistence of storage-class memory. It operates at data rates up to 3200 MT/s and is targeted at high-performance, high-capacity enterprise and data center systems.

ARM expanded its DesignStart program to include the Cortex-M3 processor. The program allows usage of the core without upfront licensing fees for evaluation and prototype development, as well as access to subsystem IP. A downloadable license is required to begin commercial development.

Cadence extended tool access for ARM’s DesignStart program, including the Cortex-M3 processor and CoreLink SDK-100 System Design Kit. DesignStart users can gain access to an evaluation trial of Cadence’s Hosted Design Solutions environment including mixed-signal tools optimized for use with Cortex-M series processors.

Arastu Systems uncorked its LPDDR3/4 DRAM Memory Controller Core, which delivers performance up to 4266 MT/s. The IP conforms to the respective JEDEC standards and is compatible with DFI3.1/4.0 PHY or a PHY from any vendor.

ChipEstimate launched a new tool for comparing multiple pieces of IP at once.

The latest version of NVM Express, the specification for accessing SSDs on a PCIe bus or across Fabrics, was released. New features in version 1.3 include the ability to flexibly assign SSD resources to specific virtual machines, bootstrap an SSD in a low resource environment, and completely erase an SSD, as well as providing better endurance for NAND-based SSDs in cloud hosting applications.

Ansys and Synopsys are teaming up to integrate Ansys’ power integrity and reliability signoff technologies with Synopsys’ physical implementation solution for in-design usage. A feedback loop between Synopsys’ PrimeTime and Ansys’ RedHawk will also be provided.

ArterisIP and ResilTech partnered on a quantitative and qualitative functional safety assessment of the ArterisIP Ncore Cache Coherent Interconnect and Resilience Package IP, as well as a complete set of ISO 26262 deliverables for multiple SoC reference designs.

Synopsys’ Design Platform and Embedded Memory IP were enabled on GlobalFoundries’ 7nm Leading-Performance (7LP) FinFET process technology. The two companies are also collaborating on DesignWare Memory Compilers for GF’s 7nm process.

Cadence’s custom/analog and full-flow digital and signoff tools were enabled for v0.5 of GlobalFoundries’ 7LP FinFET technology. The 7LP PDK is available for early customer designs.

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