A Machine Learning-Based Approach To Formality Equivalence Checking


By Avinash Palepu, Namrata Shekhar and Paula Neeley After a long and hard week, it is Friday night and you are ready to relax and unwind with a glass of wine, a sumptuous dinner and a great movie. You turn on Netflix and you expect that it will not only have plenty of pertinent suggestions for you, but also the most appropriate one based on all the previous movies and shows that you have wat... » read more

Faster Formal Verification Closure For Datapaths In AI Designs


In recent years, many longstanding assumptions about formal verification have been rendered obsolete by ever-improving technology. Applications such as connectivity checking have shown that formal can work on large system-on-chip (SoC) designs, not just small blocks. Standard SystemVerilog Assertions (SVA) have eliminated the need to learn an abstruse mathematical language for each new formal t... » read more

FPGA Equivalence Checking For A Nuclear Safety Controller


Every chip development team wants to find and fix all the bugs they possibly can in pre-silicon verification. Turning a chip to fix issues found in the bring-up lab incurs high costs and product delays; bugs found in the field are even more expensive to repair. But for some applications, including military/aerospace, implanted medical devices, and autonomous vehicles, the consequences of a faul... » read more

OneSpin Users Gather in Munich


Even more than most other high-tech companies, EDA vendors rely on their users for many aspects of their success. Of course, customers provide the revenue that fuels the business, but their influence goes far beyond that. Many features in EDA tools, and even entire categories of products, arise from working closely with advanced users. Even before traditional Beta-testing, selected users provid... » read more

High-Level Design And High-Level Verification


Not so long ago, some EDA vendors were painting a very attractive picture of chip design in the then-near future. The idea was that an architectural team would write a single description of the complete system in some high-level language, usually C/C++/SystemC, and that a new class of EDA tool would automatically partition the design into hardware and software, choosing the functionality of eac... » read more

Formal Datapath Verification


J.T. Longino, formal verification application engineer at Synopsys, drills down into how to achieve confidence in datapath designs by applying formal solvers and methods to data transformation areas of a design rather than the control path areas. https://youtu.be/n1zO3GxEZVI     See other tech talk videos here. » read more

Will FPGAs Work As Expected?


OneSpin Solutions’ Muhammed Haque Khan, product specialist for synthesis verification, digs into equivalence checking in FPGA designs and what can go wrong with FPGA designs. https://youtu.be/RFlP2Z_-Yqs » read more

The Week In Review: Design


Tools Cadence unveiled a new equivalence checking tool which features a massively parallel architecture capable of scaling to 100s of CPUs and adaptive proof technology that analyzes each partition and determines the optimal formal algorithm. According to the company, the Conformal Smart Logic Equivalence Checker provides an average of 4X runtime improvement with the same resources over the pr... » read more

Formal’s Roadmap


Formal verification has come a long way in the past five years as it focused on narrow tasks within the verification flow. Semiconductor Engineering sat down to discuss that progress, and the future of formal technologies, with [getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"]; Harry Foster, chief verification scientist at [g... » read more

The New Face of Formal


Semiconductor engineering sat down to discuss the recent growth in adoption of formal technologies and tools with Lawrence Loh, product engineering group director at [getentity id="22032" e_name="Cadence"], Praveen Tiwari, senior manager R&D, verification group at [getentity id="22035" e_name="Synopsys"], Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"], Normando... » read more

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