The Week In Review: Design

HW/SW co-simulation for FPGA; bus planning; HPC compilers; high-bandwidth networking.

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Tools
Aldec released the latest version of its Riviera-PRO verification platform, adding QEMU Bridge to enable hardware/software co-simulation of designs intended to run on SoC FPGAs. Other features include improved performance when using code containing many inline randomized calls and up to 29% faster simulation speed of UVM.

Pulsic added new features to its Unity Bus Planner for planning and routing of multiple large buses and associated repeater cells. Additions include multi-terminal bus planning at the bus guide level, dynamic optimal via patterns, automatic DRC clean bus detail creation, and bus shield insertion with interleaving.

Arm uncorked a suite for building and porting high performance computing applications, including Arm-specific Fortran and C/C++ compilers, processor-optimized math libraries, and debug and optimization tools.

Mentor launched the Sourcery CodeBench GFortran embedded compiler targeted to AMD Graphics Core Next (GCN) architectures for high performance computing applications. The GFortran compiler is an open source Fortran supporting OpenACC and OpenMP (Open Multi-Processing) parallel computing directives.

IP
Open-Silicon debuted an IP subsystem for high-bandwidth networking applications. The subsystem expands on Open-Silicon’s existing high speed chip-to-chip Interlaken interface IP to include Ethernet Physical Coding Sublayer (PCS), Flex Ethernet (FlexE) and multi-channel multi-rate Forward Error Correction (FEC) IPs targeted for Ethernet endpoint and Ethernet transport applications.

Inside Secure revealed a root-of-trust engine based on RISC-V. The customizable IP will make use of the company’s recent SypherMedia acquisition through secure provisioning capability to manage a device’s root-of-trust through its entire life cycle, and has a secure asset store coupled with a complete set of crypto engines that controls access and use of keys.

Kilopass’ NVM OTP IP reached 1000-hour qualification and characterization on the 40nm Low Power Process of Mie Fujitsu Semiconductor. The samples, across separate wafers, passed high temperature operating life (HTOL) and high temperature storage life (HTSL), memory stress tests defined by JEDEC-47H.

Faraday released its M1+ standard cell library on UMC 28HPC process. The library supports the essential multi-track cells (7T/9T/12T), multi-Vt cells (LVT/RVT/HVT), and Faraday low-power PowerSlash kit. According to the company, the library yielded a 14% reduction of silicon area, with a 43% decrease in leakage power consumption compared to others.

Socionext will offer graphics engine IP based on the company’s SoC products. The IP consists of three blocks, a capture engine that accepts multiple input formats, graphics engine with 2D processing and rich functions, and displays engine that supports up to 4K resolution.

Spin Transfer Technologies announced allowance of a United States patent application, #14/814,036, for its Precessional Spin Current (PSC) structure for MRAM. The PSC, also known as a “spin polarizer,” reduces MRAM power consumption when writing data while simultaneously improving writing speed.

Deals
Inuitive selected Synopsys’ DesignWare EV6x Embedded Vision Processor for its production NU4000 3D imaging and vision SoC, which processes multiple camera inputs with high-definition resolutions up to 4K. Inuitive cited high vector DSP and neural network performance in a minimal silicon footprint as factors in the choice.

Rambus selected Codasip’s Studio tool for automated generation of the SDK for its RISC-V security products. Rambus cited fast design space exploration and high quality of results in the automatically generated compiler toolchain.

CEA List and Synopsys are teaming up on a project for verification and hybrid emulation of automotive SoCs and systems. Intially, the project will focus on integration of Synopsys’ ZeBu Server in a multi-physics automotive simulation environment, as well as large-scale hybrid co-simulation for ADAS applications.

Events
Empowering Leadership with WIT and WISDOM: Nov. 28 at 6 p.m. in Milpitas, CA. The ESD Alliance will host a panel discussion featuring women executives from the technology sector who will address career choices for women and men, including personal branding, leadership, negotiation, networking and mentoring. The evening will be held at SEMI and begin with dinner and refreshments.

Artificial Intelligence and Convolution Neural Networks: Dec. 4, 6:30-8:30 p.m. at San Jose State University, San Jose, CA. This panel discussion, hosted by the ESD Alliance, will focus on the systems companies are building to gather data and process it to drive business operations. Jim Hogan will moderate.

Decoding Formal: Dec. 7 in San Jose, CA. This regular gathering highlighting formal verification, hosted by Oski, features talks on the application of formal for two high-performance Ethernet switches plus using formal to explore all corner cases while using highly abstract architectural models for deep analysis of design behavior.