The Week In Review: Design

Tools Synopsys debuted new versions of its circuit simulation and custom design products. FineSim SPICE provides 2X faster simulation and Monte Carlo analysis speed, CustomSim FastSPICE offers 2X speed-up for post-layout SRAM simulation and maintains multi-core scalability by providing additional 2X speed-up on four cores, and HSPICE delivers 1.5X speed-up for large post-layout designs, accord... » read more

Debugging Debug

There appears to be an unwritten law about the time spent in debug-it is a constant. It could be that all gains made by improvements in tools and methodologies are offset by increases in complexity, or that the debug process causes design teams to be more conservative. It could be that no matter how much time spent on debug, the only thing accomplished is to move bugs to places that are less... » read more

Verification Of Functional Safety

The automotive industry is grappling with a tradeoff between cost and safety. Safety is well understood in industries that are cost-insensitive, such as aerospace and medical, and the consumer industry has a long track record of driving down costs while increasing functionality. But can these two industries be brought together in a safe and effective manner to enable automobiles to achieve the ... » read more

The Week In Review: Design

Tools Imperas debuted its RISC-V Processor Developer Suite, a set of models, a software simulator, and tools to validate, verify, and provide early estimation of timing performance and power consumption for RISC-V processors. IP Minima Processor revealed its dynamic-margining subsystem IP for near-threshold voltage design. The startup's hardware and software IP works with a CPU or DSP proc... » read more

The Week In Review: Design

Tools Aldec released the latest version of its Riviera-PRO verification platform, adding QEMU Bridge to enable hardware/software co-simulation of designs intended to run on SoC FPGAs. Other features include improved performance when using code containing many inline randomized calls and up to 29% faster simulation speed of UVM. Pulsic added new features to its Unity Bus Planner for planning... » read more

How To Handle Concurrency

The evolution of processing architectures has solved many problems within a chip, but for each problem solved another one was created. Concurrency is one of those issues, and it has been getting much more attention lately. While concurrency is hardly a new problem, the complexity of today‚Äôs systems is making it increasingly difficult to properly design, implement and verify the software an... » read more

Dealing With Deadlocks

Deadlocks are becoming increasingly problematic as designs becoming more complex and heterogeneous. Rather than just integrating IP, the challenge is understanding all of the possible interactions and dependencies. That affects the choice of IP, how it is implemented in a design, and how it is verified. And it adds a whole bunch of unknowns into an already complex formula for return on inves... » read more

The Week In Review: Design

M&A Synopsys acquired materials modeling company QuantumWise. QuantumWise tools focus on atomic-scale modeling of nanostructures using quantum-mechanical computational methods, classical potentials, and electrostatic models. Based in Denmark, the company was started in 2008 when it acquired the assets of Atomistix. The technology will be integrated with Synopsys' Sentaurus TCAD. Terms of t... » read more

When Is Verification Complete?

Deciding when verification is done is becoming a much more difficult decision, prompting verification teams to increasingly rely on metrics rather than just the tests listed in the verification plan. This trend has been underway for the past couple of process nodes, but it takes time to spot trends and determine whether they are real or just aberrations. The Wilson Research Group conducts a ... » read more

How Much Verification Is Necessary?

Since the advent of IC design flows, starting with RTL descriptions in languages like Verilog or VHDL, project teams have struggled with how much verification can and should be performed by the original RTL developers. Constrained-random methods based on high-level languages such as [gettech id="31021" t_name="e"] or [gettech id="31023" comment="SystemVerilog"] further cemented the role of t... » read more

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