Blog Review: April 17

Siemens’ Sumit Vishwakarma highlights the importance of crystal oscillators to the proper functioning of many semiconductor devices and applications, from clock signals to transmission and reception of radio waves.

Cadence’s Jay Domadia introduces some of the new features in GDDR7, such as a semi-independent row and column command address bus and two modes of data signaling, enabling PAM3 for high speed and NRZ for low speed.

Synopsys’ Keivan Javadi Khasraghi and Priyank Shukla look at an effort to standardize the implementation of PCIe over fiber optics to expand ranges and data rates and reduce power requirements while keeping the field open to a broad swathe of optical technologies

Keysight’s Amit Varde suggests that adapting Git for hardware design poses distinct challenges, as the data requirements and workflows significantly differ from software development.

Ansys’ Laura Carter checks out an EV power optimization project that aims to develop an app that can constantly monitor an EV’s state of charge, identify range issues, take appropriate measures to extend vehicle range by powering down noncritical systems in the vehicle as the state of charge goes down.

Arm’s Volodymyr Turanskyy points to what’s new in LLVM 18, including performance improvements and support for additional CPUs along with checked pointer arithmetic, floating-point 8, and live VM migration extensions.

SEMI’s Cassandra Melvin considers the fractured geopolitical scene and the part increasingly strained supply chains and rising trade barriers have played in the EU’s decision to implement its Chips Act.

Plus, check out the blogs featured in the latest Low Power-High Performance newsletter:

Fraunhofer IIS/EAS’ Roland Jancke looks at key techniques for demonstrating quality, safety, and security, from unique identification to open source.

Siemens’ Hossam Sarhan and Dusan Petranovic contend that new physical verification approaches are needed to ensure the performance and reliability of superconducting ICs.

Rambus’ Emma-Jane Crozier surveys the need for more memory bandwidth and capacity spanning from data center to endpoint.

Synopsys’ William Ruby shows how optimizing the performance per watt of HPC SoCs starts when defining the architecture.

Cadence’s Shyam Sharma explores how, from gaming consoles to network switches, higher data rates are enabling low-power memory to expand beyond its traditional spaces.

Ansys’ Laura Carter explains how simulation helps manage the complexities of building and maintaining a fusion reactor test rig.

Mixel’s Ashraf Takla weights how IoT demands a balance between cloud and edge processing to optimize system performance.

Arm’s Bolt Liu presents a post-link optimizer for typical server workloads.

Quadric’s Steve Roddy explains the origins of the Chimera architecture.