Blog Review: Aug. 14

Cadence’s Dimitry Pavlovsky highlights two new features in the AMBA CHI protocol Issue G update that enhance security of the Arm architecture: Memory Encryption Contexts, which allows data in each Realm in the memory to be encrypted with a different encryption key, and Device Assignment, which introduces hardware provisions to support fully coherent caches in partially trusted remote coherent devices.

Siemens’ Farhad Ahmed finds that as multiple asynchronous resets have become the norm in large, complex designs, having a reset domain crossing sign-off methodology is necessary to avoid chip-killing metastability, glitches, and other functional problems.

Synopsys’ William Ruby discusses how the flexible nature of RISC-V calls for early power analysis to help balance the tradeoffs between the performance and efficiency benefits of extending the instruction set architecture with additional processor complexity.

Keysight’s Bernard Ang highlights waveform tools for signal processing and analysis and the key capabilities that enable design and test engineers to create complex waveforms for analog signals with fine-grained control over their shapes, durations, frequencies, phases, number of cycles, rise times, fall times, and other characteristics.

Arm’s Ed Miller shares a project that both helps developers hone their AI skills while also supporting conservation efforts by creating AI applications for camera traps that can noninvasively monitor and identify bears and other wildlife.

Ansys’ Kerry Herbert and Edmund Optics’ Cory Boone look at how the combination of AI with multiphysics simulations can provide insights that yield a better understanding of the real performance of optical systems and the ability to explore design spaces faster and more efficiently.

The ESD Alliance’s Bob Smith chats with Jeff Lewis about the early days of the IP industry, including development of the royalty model, challenges involved in initial customer adoption, and future growth of process-related IP.

And don’t miss the blogs featured in the latest Low Power-High Performance newsletter:

Arm’s Sriharsha Vinjamury finds 2nm technology offers significant performance improvements, but costs are higher and detecting defects becomes harder.

Fraunhofer IIS/EAS’ Björn Zeugmann and Benjamin Prautsch look at strategies to tackle the long development times and high costs of designing and verifying analog components.

Synopsys’ Faisal Goriawalla provides an overview of the multi-die test challenges that go beyond the design phase, covering manufacturing and deployment in the field.

Rambus’ Tim Messegee digs into the higher bandwidth needed in AI PCs and how DDR5 main memory will push to data rates of 6,400 megatransfers per second (MT/s) and beyond.

Cadence’s Frank Ferro shows how AI/ML training models are stressing existing infrastructure and driving the need for memory subsystems that support high data rates.

Ansys’ Caty Fairclough details how simulation is helping a vertical aircraft developer create a more sustainable future.

Siemens EDA’s Russell Klein points out why HLS is critical for determining which type of processors to use.