450mm wafers; chiplet time-to-market; biometric search and bug hunting; TinyML.
Cadence’s Paul McLellan wonders what’s happened to 450mm wafers as equipment development efforts end, the only wafer fab is decommissioned, and manufacturers see little likelihood to recoup further investment in R&D.
Synopsys’ Manuel Mota finds that the scale and modular flexibility of chiplets can help meet narrowing time-to-market windows and looks at how UCIe provides a complete stack for the die-to-die interface.
Siemens’ Rich Edelman dives into identifying hard-to-find bugs by determining how data is moving and not moving using biometric search with sequences of transitions and buffered, prioritized packets.
Renesas’ Eldar Sido discusses the importance of accuracy, power consumption, latency, and memory requirements when benchmarking and developing TinyML systems.
Ansys’ Angela Forcino checks out simulation of heads-up displays and ways to quantify the quality of the virtual image of automotive HUDs.
In a blog for SEMI, Advanced Energy’s Ray Morgan explains why precisely controlled, reliable high-voltage power technologies play a critical role in supporting advanced semiconductor manufacturing processes.
And don’t miss the blogs featured in the latest Systems & Design newsletter:
Technology Editor Brian Bailey warns that until learning systems are given the ability to forget, we need the reset button, and this is not sustainable.
Cadence’s Frank Schirrmeister looks back on past productivity improvements to see what can be learned for the path forward.
Synopsys’ Manoj Chacko asks why ECO has become such a dominant factor in design signoff.
Renesas’ Marta Martínez Vázquez finds that two design parameters are critical to extending the range of a radar MMIC transceiver.
Siemens’ Nermeen Hossam and John Ferguson examine the advantages of early design rule checking for selected rules and geometries.
Codasip’s Lauranne Choquin explains how to customize an existing design to create a unique processor tailored for specific applications.
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