Blog Review: Dec. 6

Synopsys’ Eric Huang examines electromagnetic interference, the Bit Error Rate in USB 3.2 and how different transfer types handle errors.

Mentor’s Nitin Bhagwath points out several things that can cause DDR signals to behave badly, from excessive ringing to stubs in the channel.

Cadence’s Paul McLellan listens in as Oski CEO Vigyan Singhal explains the basics of assertion-based verification and why formal is so different from simulation.

Intel’s Ron Wilson warns that seeking perfect IoT security can become a nearly infinite regression at nearly infinite cost, making it important to evaluate what the device is capable of and what is at stake.

Rambus’ Aharon Etengoff looks at some of the ways machine learning is being used by financial institutions, from chatbots to calculating auto insurance claims.

QuickLogic’s Timothy Saxe points to a confluence of advances that make embedded FPGAs a compelling way to add post-manufacturing design flexibility with small silicon cost.

Nvidia’s Rosie Brown gathers perspectives from 13 researchers and experts on where AI is heading in 2018, from medical applications to daily life.

Silicon Labs’ Kevin Smith continues his series on timing with an examination of the differential split circuit termination.

A Lam Research writer points out several ways semiconductors are improving health care, including remote cardiovascular disease screening and robotic surgery.

Samsung’s Anders Graham argues that SSDs are beating out HDDs in data center performance, plus shows off a video of a 3PAR 8450 All-Flash-Array built with LEGO.

Agnisys’ Uttam Sarkar says the era of semiconductor consolidation is just beginning, and will help make designs better and less expensive.

Arm’s Elan Tanzer shares the latest updates to Arm’s DS-5, including debugger improvements, Fixed Virtual Platforms, and support for baremetal performance analysis.

In a video, Cadence’s Tom Hackett explains the basics of neural networks with the help of spreadsheets.

Synopsys’ Manoj Sharma Tanikella digs into pros and cons of the Unified Memory Extension, part of the Universal Flash Storage specification which allows users to use part of the host memory as the device’s internal memory.

Mentor’s John Ferguson shares some ways to optimize performance during physical verification and improve DRC runtimes.

And for some holiday cheer, Cadence’s Meera Collier begins the story of Ben Easer, CEO of Skrooj, Inc and the Ghost of Moore’s Law in an EDA retelling of the classic ‘A Christmas Carol.’

And don’t forget the blogs featured in last week’s System-Level Design newsletter:

Editor in Chief Ed Sperling contends this week’s semiconductor stock gyrations are just the beginning.

ArterisIP’s Kurt Shuler looks at how to increase memory bandwidth and reduce latency in next-generation SoCs.

Mentor’s Prasad Tota and Analog Devices’ Robert Day find that testing every configuration of a package in a lab is practically unfeasible, but thermal simulation can help.

Cadence’s Frank Schirrmeister argues that many things could trip up the predicted explosion of connected devices, but the hurdles are not insurmountable.

Aldec’s Krzysztof Szczur observes that FPGAs are the fastest prototyping platform, and that speed can be utilized in other parts of the verification process.

OneSpin’s Sergio Marchese zeroes in on efforts to streamline certification and bring the many safety standards under a more general framework.

Synopsys’ Tom De Schutter notes that in prototyping, automation is no substitute for the experience of specialists.

eSilicon’s Mike Gianfagna finds that as chip complexity rises, it’s no longer possible for one company to do it all.

Technology Editor Brian Bailey warns that the advent of cheap, fast manufacturing and instant sales channels is overwhelming us with products, and new search methods are required to connect buyers with sellers.

XtremeEDA’s Neil Johnson considers how local news might tease a segment on UVM.