Blog Review: Dec. 9

Arm’s Benoit Labbe digs into designing a power converter for Arm Research’s ultra-low power M0N0 microcontroller, with a focus on optimal efficiency and leakage constraints.

Mentor’s Harry Foster tries to get a sense of how much effort is spent in verification of FPGAs by looking at the amount of time spent and number of engineers on a project.

Cadence’s Paul McLellan listens in as Odile Liboiron-Ladouceur of McGill University explains the challenges of building integrated photonic interconnects and processors.

Synopsys’ Ron Lowman provides an overview of 5G, the various applications expected to benefit from it, and a few of the big chip design challenges.

Ansys’ Charly Meyer takes a look at using HPC simulation to speed the design process of automotive sensors and provide easier testing of edge cases and dynamic conditions.

SEMI’s Jim Hamajima shares some key discussions happening at the upcoming, online SEMICON Japan, including a global semiconductor outlook, manufacturing for quantum computing, and changes the automotive industry.

Intel’s Anil Kumar explains Ethernet Time Sensitive Networking standards and how they can reduce network complexity, decrease networking costs, and improve security for industrial systems.

ON Semiconductor’s Bruno Damien checks out the Zigbee Alliance’s Green Power Protocol and new potential for low power, energy harvesting industrial IoT systems.

And don’t miss the blogs featured in the latest Automotive, Security & Pervasive Computing and Test, Measurement & Analytics newsletters:

Editor in Chief Ed Sperling contends that the age of purely mechanical industrialization is over, and the new data-driven electro-mechanical age is here.

Arteris IP’s Kurt Shuler warns that interpreting the ISO 26262 functional safety standard isn’t as simple as just looking at the document.

Flex Logix’s Geoff Tate lays out what matters for different customers in the rapidly growing edge inference market.

Mentor’s Nigel Hughes explains adopting a model-based approach to seamlessly leverage data from development stages to drive downstream processes.

Rambus’ Thierry Kouthon advocates for anchoring security in hardware to protect the security of safety-critical ECUs and sensors.

Cadence’s Paul McLellan looks at how to extend existing architectures with capabilities to improve memory security.

Synopsys’ Taylor Armerding digs into how managing security vulnerabilities and false positives can improve DevSecOps.

Editor in Chief Ed Sperling contends that while reliability at 3/2nm and smaller is technologically possible, the whole industry may have to change to get there.

YieldHub’s Marie Ryan explains the parts that make up a complete and fully compatible STDF or ATDF file.

Synopsys’ Stephen Crosher describes building a foundation to monitor, analyze, and optimize semiconductor devices throughout design, manufacture, test, and deployment.

FormFactor’s Peter Andrews lays out what to know to eliminate costly tool deployment issues inherent with low noise TestCell optimization.