AI predictions; Python and SystemVerilog tips; CFD and chip design; neural net optimization.
Synopsys’ Stelios Diamantidis shares some predictions for AI in 2022, including the three markets that will push new AI chips, the increasing need for trust chains, the entry of non-traditional companies, and the impact of AI in chip design.
Siemens EDA’s Ray Salemi checks out how Python and SystemVerilog can work together to boost the verification ecosystem by taking advantage of what each has to offer.
Cadence’s Paul McLellan finds out how computational fluid dynamics relates to software development and chip design with an increasing reliance on highly-parallel matrix and graph analysis.
Arm’s Elham Harirpoush provides a primer on optimization techniques for neural networks such as quantization, pruning, and clustering, and how to use the TensorFlow Model Optimization Toolkit to tune a model for the Ethos-U microNPU.
Ansys’ Shawn Carpenter examines the recent conflict between the aviation industry and telecom industry with the roll out of 5G near airports potentially having an impact on the radar altimeters used to assist with low-visibility landing.
SEMI’s Hiroki Yomogita shares highlights from the recent SEMICON Japan event as industry leaders focused on the need for collaboration, closer ties, greater openness, and more flexibility to co-innovate solutions.
Memory analyst Jim Handy examines the different processor-in-memory approaches being taken and the key market considerations that will determine the likelihood of commercial success.
And don’t miss the blogs featured in the latest System & Design newsletter:
Technology Editor Brian Bailey contends that verification can be done better and faster, using less energy, if we throw out today’s unethical coverage metrics.
Cadence’s Frank Schirrmeister looks at big trends from the last decade that are still in full swing.
Synopsys’ Hari Sathianathan explains how to formally verify embedded memory designs and their redundancy repair schemes.
Siemens’ Pirzad Motafram investigates why coverage and assertion tools are vital to ensuring ICs are production-ready.
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