Blog Review: Jan. 15

Siemens EDA’s Stephen V. Chavez argues that the placement of decoupling capacitors on a PCB can make or break a design’s power delivery system and provides some best practices and design considerations, such as ensuring even distribution on a board rather than crowding them around chips.

Synopsys’ Stelios Diamantidis predicts that in 2025, AI agents will begin collaborating with other AI agents to bring together individual industry- and workflow-specific functions and provide the ability to combine and analyze data across the chip design flow.

Cadence’s Vishnu Teja S provides a high-level overview of the analog IC design flow from design specifications to GDSII.

Keysight’s Ben Miller introduces the basics of PCIe protocol testing and how protocol analyzers and exercisers work in tandem to enable deterministic testing of all PCIe scenarios.

Ansys’ Akanksha Soni provides a primer on ISO 26262 and notes the complexities finFET designs and 2.5D/3D-IC advanced packaging technologies require multiphysics simulation to ensure they meet the standard.

Arm’s Paul Black uncorks Arm Toolchain for Embedded, an open source embedded C/C++ cross-compiler supporting high-performance projects with optimization for 64-bit cores and full migration to LLVM.

The ESD Alliance’s Bob Smith chats with Accellera’s Lu Dai about new standards, including work on federated simulation, functional simulation, and a mixed-signal interface for SystemVerilog, and takes a peek at potential efforts on the horizon such as an AI data format for EDA and supply chain security.

Plus, check out the blogs featured in the latest Automotive, Security & Pervasive Computing and Test, Measurement & Analytics newsletters:

Rambus’ Bart Stevens points to key questions to consider when building a threat assessment.

Imagination’s Pallavi Sharma looks at why today’s ECUs need to have the performance and flexibility to run workloads for the next decade.

Infineon’s Rahul Raj Sharma explains what’s included in the new Matter specification and why it’s important.

Siemens’ Matthew Hogan shows how timely identification of issues can prevent future design inefficiencies or integration challenges.

Cadence’s Veena Parthan unearths some seasonally inspired fluid dynamics examples.

Onto Innovation’s Keith Best looks at the feasibility of organic and glass substrates in light of ever-shrinking line/space requirements.

PDF Solutions’ John Kibarian explains why increasing engineering efficiency will require lowering the AI expertise barriers for everyone in the chip industry.

Teradyne’s Jeorge Hurtarte digs into standards that are paving the way for more efficient, reliable, and collaborative semiconductor testing processes based on access to real-time test data.

proteanTecs’ Ziv Paz explores a standardized approach to gathering critical data on system health, enabling designers to fine-tune performance and prevent failures.

Advantest’s Ken Butler shows how accurately modeling DPPM allows engineers to make decisions that affect the tradeoffs between test effort and product quality.

Siemens’ Peter Orlando examines a bus-based scan distribution architecture that provides a scalable method for concurrently testing identical and non-identical cores.