Blog Review: Jan. 31

Cadence’s Paul McLellan looks back at where TSMC was 30 years ago and the founding philosophy that made the foundry and fabless model work.

In a video, Mentor’s Colin Walls considers how to make the simplest possible multitasking scheduler with a one line RTOS.

Synopsys’ Sandeep Taneja checks out the technology behind airbags in cars and the role of the Motorola Serial Peripheral Interface in coordinating sensors.

Aldec’s Vatsal Choksi dives into UVM with a tutorial on how communication takes place from sequence to sequencer and from sequencer to driver.

Arm’s Jim Wallace explains why machine learning is moving to edge devices and why running neural networks on CPUs can sometimes be an advantage.

A Lam Research writer checks out trends powering the data storage market, which is expected to account for 7.5% of semiconductor revenue by 2020.

Will AI take over all the jobs? Rambus’ Aharon Etengoff looks at the confusion of AI with automation and where the former could spur job creation.

Silicon Labs’ Kevin Smith digs into timing issues with an examination of spurs in clock phase noise measurements.

Applied’s Max McDaniel notes that display technologies were everywhere at CES this year and takes a look at the technologies behind them, from OLED to MicroLED to HDR.

Nvidia’s Jamie Beckett points to a project to improve mammogram readings with a neural network that can more accurately distinguish between benign and cancerous characteristics.

NXP’s Jim Norling considers the challenge to cellular communications infrastructure that will come with the Super Bowl.

Synopsys’ Samantha Beaumont takes a look at the major changes to online privacy regulations, which aim to give EU residents more control over how their personal data is used.

In a video, Cadence’s Nick Heaton describes the verification challenges for SoCs when integrating CCIX interface IP.

Mentor’s Tarek Ramadan considers the need for automated layout vs. schematic verification when it comes to high density advanced packaging.

Plus, don’t miss the highlighted blogs from last week’s System-Level Design newsletter:

Editor In Chief Ed Sperling contends that the creation of new markets for semiconductors could help iron out demand fluctuations.

Technology Editor Brian Bailey points to what’s changing at DVCon this year and who should attend.

Mentor’s Mark Olen finds that SoC development has hit a bottleneck when it comes to re-using verification stimulus.

OneSpin’s Sergio Marchese explains why more engineers want to become experts in formal verification.

Synopsys’ Ruben Molina observes that new transistor architectures also mean new parasitic effects to watch out for.

Cadence’s Frank Schirrmeister details why sharing expertise is necessary for a robust SoC ecosystem.

Aldec’s Sunil Sahoo compares waveform analysis to data plots.

eSilicon’s Mike Gianfagna zeroes in on what’s ahead for advanced ASICs.