Blog Review: July 14

Siemens EDA’s Wei-Lii Tan considers the tradeoffs when running library characterization in the cloud and how to think about running CPUs in parallel, the cost of throughput, and runtime reductions.

A Synopsys writer checks out the reduced blanking feature in HDMI 2.1, which can help reduce the transmission rate while keeping the resolution and refresh rate intact for higher resolution displays at low power.

Cadence’s Paul McLellan learns about ‘hot’ quantum computing from Jason Lynch, COO of Equal1, which has developed a quantum processor running at 3.7K and based on a commercially available CMOS process, plus challenges with decoherence and the startup’s next steps.

Arm’s Simon Tatham introduces an open-source code base for analyzing and browsing trace files in Tarmac trace format top make it easier to get a look at exactly how a CPU is behaving.

The ESD Alliance’s Bob Smith chats with Jean-Marie Brunet of Siemens EDA about the challenges in verifying increasingly complex SoCs and the opportunities for hardware-assisted verification to integrate hardware and software earlier in the process.

Memory analyst Jim Handy explains why migrating NAND flash to the next number of bits as soon as possible isn’t necessarily an optimal choice, with diminishing cost advantages and challenges in endurance and error correction.

Ansys’ Matt Commens introduces new meshing technology in the company’s high-frequency electromagnetic simulation software that uses local knowledge of the geometry to perform locally optimized meshing techniques for those geometries.

Nvidia’s Adam Grzywaczewski notes that while great progress has been made in natural language processing for a few languages, efforts are needed to expand it to other common languages such as Hindi, Arabic, and Spanish where NLP performance is poor.

And don’t miss the blogs featured in the latest Low Power-High Performance newsletter:

Siemens EDA’s Harry Foster examines the relationship between verification maturity and non-trivial bug escapes into production and the effect of safety-critical design practices on the level of silicon success.

Arm’s Eddie Ramirez argues for thinking outside the data center to bring computing closer to users.

Synopsys’ Manu Verma explains the importance of getting the right mix of analog and digital blocks for best performance, lowest power, and smallest area.

Cadence’s Paul McLellan reports that the applications enabled by hyperscale computing are seen by most consumers as positive, while data privacy and security concerns remain.

Ansys’ Sean Patterson digs into the design of lidar systems.

Rambus’ Tim Messegee lobbies for moving beyond the classic architecture of the server through disaggregation and composability.

Infineon’s Suresh Thangavel lays out why SiC MOSFETs improve power conversion efficiencies and lower system costs for solar and battery storage applications.

Fraunhofer’s Olaf Enge-Rosenblatt and Andy Heinig examine when can AI methods be used effectively from the user perspective.

Infineon’s Jeff Kelley describes using a layered approach for increasingly connected vehicles.

Rambus’ Gus Willemse illustrates the impact of disaggregation on security.

Synopsys’ Hari Sathianathan demonstrates how to handle verification of power-aware library cell models with internal state dependencies.