Interconnect warnings; brain freezers; sensors; tariffs; AMS; questions from India.
By Ed Sperling
Wherever you turn in IC design, there’s always someone talking about future problems involving the interconnect. Cadence’s Brian Fuller puts the latest speech by North Carolina State professor Paul Franzon in historical perspective—or at least in the shadow of the last dire prediction by Intel’s Mark Bohr two decades ago. Incidentally, Bohr’s warning turned out to be right.
Mentor’s Mark Olen looks at an interesting development in verification—the need to verify hardware and software interactions. The graphic will make your brain hurt.
Synopsys’ Mike Thompson examines the new world of sensors—more complex, faster, lower power—and they’re literally everywhere.
IHS iSuppli’s Glenn Gu looks at China’s antidumping tariffs and what effect they will have on polysilicon pricing. Answer: Not much.
Cadence’s Richard Goering breaks PCIe over M-PHY into digestible chunks of information, including why this stuff is important, with some links to dig much deeper when you’ve had a second cup of coffee.
Mentor’s Harry Foster uncorks part seven of the Wilson Research verification study, this segment on testbench characteristics and simulation strategies. Check out the shift in constrained random simulation.
Synopsys’ Richard Solomon dips into direct memory access controllers and some best practices and tips for working with them and when to consider using them. This is an interesting system-level tradeoff discussion.
Mentor’s Colin Walls offers some advice to young engineers in India in an interview. The questions on this one are as interesting as the answers because they provide insights into where the pain points and perceived pain points are among engineers there. http://chetanpatil.info/1/post/2013/07/interview-with-colin-walls.html
Synopsys’ Helene Thibieroz has issued a call for AMS papers for DesignCon 2014. This may sound like jumping the gun, but proposals are due next week and full papers are due in mid-November.
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