Blog Review: June 4

In a podcast, Siemens’ Conor Peick, Dale Tutt, and Mike Ellow chat about the implications of the software-defined transition, how it affects semiconductor development, and why it seems to be leading more companies towards developing their own silicon.

Cadence’s Vinod Khera shows off a Linux-based audio development platform for prototyping AI audio applications with support for real-time audio processing and low-latency DSP tasks.

Synopsys’ Simon Han checks out how Skymizer used FPGA-based prototyping to design AI accelerator IP and validate multimodal AI workflows at speed.

Lam Research’s Jacky Huang and Sandy Wen use virtual fabrication to track the evolution of stress deformation during finFET polysilicon sacrificial gate creation and removal to evaluate whether these deformations would lead to process module failures.

Keysight’s Emily Yan points out that AI data centers are fundamentally different from traditional infrastructure and require different test methods, highlighting three core challenges network architects face that can derail performance and ROI as AI data centers scale.

Arm’s Volodymyr Turanskyy highlights what’s new in LLVM 20, from new architecture and CPU support to a number of code generation improvements.

Ansys’ Adam Norman explains how rapid octree meshing technology eliminates the need for a separate surface meshing step to enable faster creation of larger, more realistic models and simulations with meshes in the range of hundreds of millions to billions of cells.

SEMI’s Iranda Chaki looks for opportunities for the European semiconductor industry in a rapidly changing geopolitical landscape where export controls, investment screening mechanisms, and economic security strategies are no longer abstract policy discussions.

Plus, don’t miss the blogs featured in the latest Systems & Design newsletter:

Brian Bailey queries whether large EDA companies are ignoring some of the benefits of the Design Automation Conference, as its funding shrinks, the event shortens, and attendance drops.

Siemens’ Shetha Nolke examines the causes of mechanical failures in 3D-ICs.

Synopsys’ Larry Lapides outlines a plan for multiple complementary verification methodologies for different levels of RISC-V processor integration.

Keysight contributor Michelle Clancy Fuller examines the impact of disaggregation on verification.

Cadence’s Vanessa Do explores the benefits of CXL architecture in memory expansion and sharing for AI, while ensuring data consistency within the fabric.

Arteris’ Insaf Meliane explains how to eliminate hardware-software mismatches and ensuing design re-spins of complex SoCs.

Alphawave’s Shivi Arora and Sue Hung Fung explain how to share data efficiently between CPU cores, accelerators, and other components.