Blog Review: Mar. 19

Cadence’s Neelabh Singh explains the defined port operations of USB4 that are used to bring transmitters burst and receivers of a design under test into compliance mode and to execute tests like bit error tests, error rate tests, clock switch tests, TxFFE equalization tests, and electrical idle tests.

Siemens EDA’s Stephen V. Chavez examines the use of blind and buried vias in high-density interconnect PCB design, which enhance routing capabilities by freeing up additional routing resources, increasing the amount of routing channels while requiring fewer signal layers, and optimizing board space.

Synopsys’ John Rogers points to key aspects of optical design that have seen remarkable advancements over the last 25 years, including color correction, direct optimization of as-built performance, modal analysis, and optimization over pressure and temperature.

Ansys’ Marc Swinnen warns that analysis and debug of analog interconnect parasitics too often rely on a patchwork of vendors and point tools that fail to address the growing complexity of multiphysics requirements with any clear strategy.

Keysight’s Nancy Friedrich explores the RF engineering behind satellite communications systems, from how the key components function together to the impacts of frequency band selection and the various natural and technical challenges that designers face.

Arm’s Lucas Bressan explains some of the complexities involved in meeting the requirements of the ISO/SAE 21434 standard for automotive cybersecurity and why it is necessary to go all the way back to IP suppliers to ensure processes are in place for secure development and vulnerability management.

SEMI’s Sherrie Gutierrez chats with Mung Chiang of Purdue University about the growing semiconductor industry in the Midwest and the importance of collaboration between industry and academia to advance semiconductor innovation and address workforce challenges.

Ayar Labs’ Mark Wade traces the company’s startup journey as it faced gaps in manufacturing, assembly, and test infrastructure coupled with the lack of a high-volume market application and looks ahead to the impact of optical interconnects on large-scale AI systems.

And don’t miss the blogs featured in the latest Low Power-High Performance newsletter:

Power architect Barry Pangrle delves into the papers presented at ISSCC about an approach that improves energy efficiency and reduces power using three coupled control loops.

Synopsys’ Vin Liao and Robert Ruiz explain how to make each iteration of the compile-run-debug loop shorter by replacing the design with an automatically generated testbench stub.

Rambus’ Raj Uppala looks at key improvements in MIPI’s Camera Serial Interface 2 protocol, such as an always-on sentinel conduit and unified serial link encapsulated transport.

Siemens’ Pratyush Kamal explores how AI optimization engines can play a role in finding optimized global solutions across multi-variate problems.

Cadence’s Pamula Sai Srinivas illustrates the importance of choosing the appropriate drive strength to meet timing constraints while minimizing power and area.

Ansys’ Ka-lip Chu digs into the importance of safety analysis and the challenges in meeting the ISO 26262 standard and Automotive Safety Integrity Levels.

Arm’s Máté Stodulka and Tomas Zilhao Borges show how to predict dynamic behaviors in a physics system in a way that’s computationally efficient and adaptable to a range of scenarios.

Quadric’s Steve Roddy details porting challenges in new and complicated transformer models aimed at advanced automotive use cases, such as enhanced object detection and recognition in L3/4/5 ADAS.