Blog Review: Mar. 27

Rambus’ Steven Woo takes a look at the memory requirements of neural networks and why some companies are using on-chip memory while others are using HBM2 or GDDR6.

Cadence’s Lana Chan  observes growing momentum for NVMe and highlights some new features in the latest specification that are pushing mainstream adoption forward.

Mentor’s Matthew Ballance contends that when it comes to adopting Portable Stimulus, selecting the right first step is crucial to finding long-term success.

Synopsys’ Prishkrit Abrol checks out what’s new in the USB4 specification, including higher speed, Thunderbolt, and bandwidth optimization mechanisms.

Arm’s Francisco Socal explains the company’s approach to accelerators and device virtualization, plus introduces a set of system architecture layers for interfacing accelerators and I/O devices while the industry works to identify a standardized solution.

Lam Research’s Steve Proia checks out what goes into making a silicon wafer, from how sand gets purified to creation of a single perfect crystal, and some ways its used outside of semiconductors.

Intel’s Ron Wilson contends that when its necessary to update embedded systems, there are times when it makes sense to absorb smaller or older CPUs into even a low-end FPGA.

Walt Custer of Custer Consulting Group warns that 2019 is off to a weak start with a look at the current state of equipment shipments, semiconductor sales, and passive components.

ANSYS’ Joao Geada argues that margin-based techniques aren’t enough to ensure optimal performance of 7nm finFET designs and that multiphysics effects impacting timing signoff, power integrity and thermal reliability should be taken into account.

Plus, check out the highlighted blogs from last week’s Manufacturing, Packaging & Materials newsletter:

Editor In Chief Ed Sperling examines the drivers for the next wave of disruptions in chip manufacturing.

Editor Mark LaPedus reports a wave of mergers are occurring in electronic materials amid a sea of change.

Applied Materials’ Matt Cogorno and Toshihiko Miyashita explain why trimming fins after dummy gate removal reduces deformation and improves power, performance and area/cost.

SEMI contributor and IHS Markit analyst Manuel Tagliavini sees 3D optical sensing now ramping up beyond high-end smartphones.

Semico Research’s Adrienne Downey describes the state of new fabs and wafer capacity expansion amid a slowing memory market.

Coventor’s Benjamin Vincent shows how to reduce the inherent patterning failure rate to less than 1%.