Blog Review: Mar. 6

Synopsys’ Gandharv Bhatara notes that successfully deploying high-NA EUV will rely on computational lithography to provide accurate modeling of aberrations, compact 3D mask modeling, and expand inverse lithography to full-chip processing.

Cadence’s John Park argues for using a systematic and automated system for co-design and co-analysis of multi-die packages to reduce the margin for human error and analyze the interactions between the ICs, dies, their package, and their PCB.

Siemens’ John McMillan finds that high-density advanced packaging requires enhanced checking to verify that the physical die are placed correctly to ensure proper connectivity and electrical behavior.

Arm’s Dennis Laudick expects that the scale of technical complexity that will come with software-defined vehicles will require the automotive industry to come together and collaborate on foundational computing standards and frameworks.

Ansys’ Raha Vafaei explains how co-packaged optics aims to address growing challenges around bandwidth density, communication latency, copper reach, and power efficiency in data-hungry networks by bringing key elements needed for communication closer together.

Keysight’s Jenn Mullen provides a primer on quantum computers, potential applications, and challenges such as decoherence and quantum error correction.

The ESD Alliance’s Bob Smith and Silicon Assurance’s Pavani Jella warn that addressing hardware security threats during semiconductor design will require the industry to rethink how designs are conceptualized and developed so that vulnerabilities can be mitigated as early as possible.

Plus, check out the blogs featured in the latest Systems & Design newsletter:

Technology Editor Brian Bailey contends that with the disappearance of the ITRS roadmap, the industry lacks a unified voice to identify future EDA needs for timely implementation.

Movellus’ Barry Pangrle summarizes IC industry predictions that generative AI could enable more productivity and better designs.

Keysight’s Emily Yan looks at how wide-bandgap semiconductors could redefine design and simulation workflows for the next decade.

Arteris’ Frank Schirrmeister shows that significant effort is involved in developing coherent NoCs from scratch.

Dana Neustadter (Synopsys), Ruud Derwig (Synopsys), and Martin Rösner (G+D) point to the deployment of an integrated SIM as a tamper-resistant secure element in a baseband SoC.

Cadence’s Anika Sunda underscores how verification plan quality significantly influences project outcomes.

Siemens EDA’s Terry Meeks digs into how earlier design-stage error detection and correction improves the efficiency of the IP design process.