Blog Review: May 18

Coventor’s Gerold Schropfer considers taking an approach from the early days of computing and using MEMS technology to create computers based on micro-scale electro-mechanical logic and memory for emerging low-energy computing applications such as autonomous sensor nodes and edge computing.

Synopsys’ Morten Christiansen explains how USB4 differs from USB 3.2, allowing simultaneous host-to-host, PCIe, DisplayPort audio/video, and USB data on the same link and USB Type-C connector, and describes the attributes of the USB4 host, hub, dock, and device.

Cadence’s Paul McLellan finds out that the silicon photonics revolution is underway, including what’s driving it, the evolution of the form factors, and the potential of silicon lasers.

Siemens’ Katie Tormala points to four PCB thermal modeling level approaches that require different inputs, offer different information, and are useful at different phases of design.

In a podcast, Ansys’ Josh Poley, Curt Chan, and Mary Kate Joyce chat with Walt Hearn about the role simulation plays in autonomous transportation and how the technology develops for cars is getting applied to other vehicles, such as boats, trains, and other industries like healthcare.

SEMI’s Michael Hall considers fab capacity growth over the next two years and the prospects for the chip industry to reach $1 trillion in revenue by 2030.

Nvidia’s Arash Vahdat and Karsten Kreis review three techniques for overcoming the slow sampling challenge in diffusion models, a class of generative adversarial networks that can be used to synthesize novel data and images based on real data with high sample quality and mode coverage.

NXP’s Tobias Schneider, Joppe W. Bos, Christine Cloostermans, and Joost Renes look at how past difficulties with securely deploying cryptographic implementations relate to the upcoming transition to post-quantum cryptography and some of the novel challenges for cryptographic infrastructure.

Arm’s David Lecomber provides a brief history of how the company entered into and expanded in the high-performance computing market.

And don’t miss the blogs featured in the latest Low Power-High Performance newsletter:

Fraunhofer’s Andy Heinig finds that even large and complex chiplet structures can be designed reliably and efficiently.

Arm’s Lucas Bressan looks at what’s needed for safe, more power-efficient robots.

Rambus’ Tim Messegee observes that bringing signaling to 64 GT/s required some of the most fundamental changes yet to the PCIe standard.

Siemens EDA’s Himani Kaushik digs into the shortcomings of traditional block storage and points to two SSD namespace alternatives.

Synopsys’ Madhumita Sanyal weighs in on space limitations, co-packed optics, and signal integrity in Ethernet switches for hyperscale data centers.

Cadence’s Paul McLellan summarizes the latest efforts to build a common, interoperable infrastructure for radio access networks.