Blog Review: May 22

Analog behavioral modeling; package substrate design; AIoT requirements; testing 5G.


Cadence’s Sree Parvathy introduces Verilog-A, a high-level language that uses modules to describe the structure and behavior of analog systems and enables the top-down system to be defined before the actual transistor circuits are assembled.

Siemens’ Keith Felton suggests the process of package substrate design is improved by leveraging the collective expertise of multiple design domain specialists working concurrently in real-time.

Synopsys’ Hezi Saar expects the integration of AI capabilities into IoT devices to drive demand for high-performance and low-latency memory interfaces on low leakage nodes and points to some of the different power-saving approaches that can be used depending on how the AIoT device is charged.

Keysight’s Xiang Li finds that 5G protocol testing is key to ensuring standards compliance, interoperability, and network reliability, and looks at some key 5G protocol stacks and how they are tested.

Ansys’ Jennifer Procario checks out the new potential for nickel-iron batteries as an integrated solution for both energy storage and as an electrolyzer for hydrogen production that splits water into hydrogen and oxygen when charged.

Arm’s Tamar Christina shares a number of new optimizations in the GCC 13 compiler, including bitfield vectorization, add/sub optimization, min/max chaining, and support for Decimal Floating Point in the Binary Integer Decimal format.

SEMI’s Linda Tan highlights growth in Southeast Asia’s semiconductor industry and why collaboration between the companies and countries in the region is necessary to strengthen the ecosystem’s resilience and the collective competitiveness in the global market.

Plus, check out the blogs featured in the latest Low Power-High Performance newsletter:

Fraunhofer IIS/EAS’ Andy Heinig discusses why energy consumption needs to be reduced and how this can be achieved by striking a balance between universal and highly specialized architectures.

Siemens EDA’s Russell Klein talks about building a bespoke solution for inference on embedded systems.

Synopsys’ Gordon Cooper shows how smaller models with fewer parameters put image generators and chatbots within reach of an embedded NPU implementation.

Rambus’ Tim Messegee talks about the advantages of moving power management from the motherboard to the DIMM, such as helping to solve the problem of IR drop.

Cadence’s Kira Jones highlights the Tiny Tapeout program, which enables students and hobbyists to get a design fabricated at a fraction of the usual cost.

Ansys’ Adarsh Chaurasia digs into materials discovery and production, including the path towards integrated computational material engineering (ICME) and a partnership with Schrödinger to address material-to-system challenges.

Arm’s Hristo Belchev explains how the memory partitioning and monitoring (MPAM) Arm architecture supplement allows for processes to function in isolation.

Quadric’s Steve Roddy delves into the slowdown caused by conventional AI/ML inference silicon designs that employ a dedicated, hard-wired matrix engine, or NPU, paired with a legacy programmable processor.

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