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Blog Review: May 27

Practical verification; neural network history; don’t cut security; serverless computing.

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Mentor’s Neil Johnson takes a look at achieving a practical verification methodology starting with an exclusively constrained random flow and building up by adding techniques and gauging the consequences.

Cadence’s Paul McLellan explains the history of neural networks and how we’ve been trying to mimic the brain for decades, only to see funding dry up until a sudden resurgence of annotated images gave the concept fresh life.

Synopsys’ Taylor Armerding argues that now is not the time to cut budgets for application security testing, especially with a big jump in phishing attacks and related cybercrime.

Arm’s Luis E. Peña explains why serverless computing is the latest evolution of server resource virtualization and how function-as-a-service models change how people think about infrastructure.

Ansys’ Ghita Zouiten considers the disinfecting properties of ultraviolet light and how simulation could help design more effective processes and equipment that is easier to disinfect.

In a blog for SEMI, analyst Walt Custer considers the impact of the global manufacturing slowdown driven by COVID-19 on the electronic supply chain.

NXP’s Jeff James points to the growing adoption of Wi-Fi 6 in automotive and the benefits it could provide to consumers, even alongside 5G.

Nvidia’s Kevin Deierling notes that data processing units, or DPUs, should be considered differently from CPUs or GPUs and are newly essential to data centers.

And don’t miss the blogs featured in the latest Manufacturing, Packaging & Materials newsletter:

Editor In Chief Ed Sperling points to a surge in complexity of materials used at 5nm and beyond.

SEMI’s Heidi Hoffman walks through how to help offices recover and repopulate by identifying risks in a crisis and ensuring safety.

Lam Research’s Steven T. Mayer, Bryan Buckalew, and Kari Thorkelsson explain how to achieve high-quality, smooth surfaces at the tops of the megapillars and uniform megapillar height across the wafer.



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