Blog Review: Sept. 25

PCIe 6.1 flow control; formal basics; cloud EDA boosts time to market; testing PCB interconnects with boundary scan; open-source RNG for AI.

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Cadence’s Mamta Rana digs into how PCIe 6.1 ECN builds on the FLIT-based architecture introduced in PCIe 6.0, further optimizing flow control mechanisms to handle increased data rates and improved efficiency but making verification of shared credit updates essential.

Siemens’ Nicolae Tusinschi provides a primer on formal verification, including what makes it different from simulation, practical limitations, and bounded proofs.

Synopsys’ Vikram Bhatia checks out why chip startups are turning to cloud-enabled chip development solutions to accelerate time to market by reducing the time it takes to set up a new EDA environment, per-minute licensing, and simplifying foundry audits.

Keysight’s Choon-Hin Chang points to boundary scan testing, a technique for testing interconnects on PCBs without the need for physical test probes, as a way to enhance board test coverage while being more cost-effective than standard PCB testing methods like in-circuit testing.

Arm’s Kevin Mooney introduces an open-source Random Number Generator (RNG) library that targets targeting performance improvements for AI frameworks and developers of scientific applications and financial software and aims to make it easier to port applications to Arm by being a drop-in replacement for the random number generation component of Intel’s Vector Statistics Library.

Ansys’ Susan Coleman highlights a project at Nagoya University that uses computational fluid dynamics to analyze the diverse fin morphology and hydrodynamics of cetaceans, which includes dolphins and whales, to help understand the evolutionary process of how and why they acquired their fin shapes.

SEMI’s Maria Daniela Perez chats with Mark Puttock of Entegris about the challenges of scaling SiC power chip manufacturing from a material supplier’s perspective and why the hardness of SiC poses a particular hurdle for chemical mechanical planarization processing.

Plus, check out the blogs featured in the latest Manufacturing, Packaging & Materials newsletter:

Amkor’s InRak Kim shows how epoxy molding compound materials can affect carrier and package warpage.

Lam Research’s Pradeep Nanja determines the impact of CT recess depth and critical dimensions on source/drain to via series resistance.

Tignis’ David Park contends that maintaining robust production capabilities for mature nodes is more important than ever.

Calibra’s Jan Willis digs into photomask trends, including advancements in multi-beam e-beam and laser writers and the development of EUV actinic mask inspection equipment.

SEMI’s Melissa Grupen-Shemansky, Pushkar Apte, and Mark da Silva look at the path to Industry 4.0 and a vision of Industry 5.0, integrating human creativity with robotic precision enabled by AI.



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