What’s Next In R&D?


Luc Van den hove, president and chief executive of Imec, sat down with Semiconductor Engineering to discuss R&D challenges and what’s next in the arena. The Belgium R&D organization is working on AI, DNA storage, EUV, semiconductors and other technologies. What follows are excerpts of that conversation. SE: Moore’s Law is slowing down. And it is becoming more expensive to move fr... » read more

Etch Techniques for Next-Generation Storage-Class Memory


Chipmakers make abundant use of two very different functional classes of memory in their products. For operational use (main/primary memory) where speed is critical, DRAM and SRAM are employed, whereas for long-term storage, flash memory – in particular NAND – provides the high capacity at low cost needed. For both classes, efforts to improve speed, capacity, and power usage are ongoing. To... » read more

What Else Is In A Node?


In part one of this blog, I reported on the 2018 Industry Strategy Symposium (ISS) where Dan Hutcheson of VLSI Research led a panel with representatives of Synopsys, NVIDIA, Intel, ASML and Applied Materials. The participants discussed how the industry is focused on simultaneously squeezing more capabilities from leading-nodes, inter-nodes and trailing-nodes to drive advances in computing. I to... » read more

Quantum Computing Becoming Real


Quantum computing will begin rolling out in increasingly useful ways over the next few years, setting the stage for what ultimately could lead to a shakeup in high-performance computing and eventually in the cloud. Quantum computing has long been viewed as some futuristic research project with possible commercial applications. It typically needs to run at temperatures close to absolute zero,... » read more

System-In-Package Vs. eNVM


The booming automotive and IoT markets are driving increasing demand for microcontrollers (MCUs). Recent forecasts project that the overall MCU compound annual growth rate (CAGR) will reach 4% over the next five years, and in particular the automotive MCU CAGR could reach close to 14%. Non-volatile memory (NVM) is a critical element of MCUs, as it is needed not only to store the code, but al... » read more

Dealing With Resistance In Chips


Chipmakers continue to scale the transistor at advanced nodes, but they are struggling to maintain the same pace with the other two critical parts of the device—the contacts and interconnects. That’s beginning to change, however. In fact, at 10nm/7nm, chipmakers are introducing new topologies and materials such as cobalt, which promises to boost the performance and reduce unwanted resist... » read more

Combining Human Intelligence And Smart Machines


By Nancy Greco, Dave Mayewski, James Moyne, Paul Werbaneth The spacecraft Discovery and its HAL 9000 computer system had a digital twin. Stanley Kubrick’s seminal film “2001: A Space Odyssey” had its theatrical release 50 years ago this April. “2001” isn’t just a great science fiction film. Rather, it’s a great work of cinema overall, across any category. (The American Film... » read more

Tech Talk: Connected Intelligence


Gary Patton, CTO at GlobalFoundries, talks about computing at the edge, the slowdown in scaling, and why new materials and packaging approaches will be essential in the future. https://youtu.be/Zbz0R_yFFrQ » read more

Can AI Alter The Burgeoning Design Cost Trend?


Everyone in the semiconductor design arena has experienced or at least observed the impact of increasing costs for complex SoC silicon. Semico’s recently released report entitled "Silicon and Software Design Cost Analysis" reveals the cost associated with a first time design effort for a high-end, advanced performance multicore SoC using 7nm process technology can top $195M for both the silic... » read more

Big Trouble At 3nm


As chipmakers begin to ramp up 10nm/7nm technologies in the market, vendors are also gearing up for the development of a next-generation transistor type at 3nm. Some have announced specific plans at 3nm, but the transition to this node is expected to be a long and bumpy one, filled with a slew of technical and cost challenges. For example, the design cost for a 3nm chip could exceed an eye-p... » read more

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