Etch Techniques for Next-Generation Storage-Class Memory

New approaches for cloud computing and mobile applications.


Chipmakers make abundant use of two very different functional classes of memory in their products. For operational use (main/primary memory) where speed is critical, DRAM and SRAM are employed, whereas for long-term storage, flash memory – in particular NAND – provides the high capacity at low cost needed. For both classes, efforts to improve speed, capacity, and power usage are ongoing. To this end, DRAM continues traditional planar scaling to pack as many bits as possible into a given area. However for NAND devices, architectures have switched from 2-dimensional arrays to 3-dimensional stacks to address the performance challenges of further scaling.

Despite these advances, applications like cloud computing and the latest mobile products are driving need for a new memory category that combines DRAM’s speed with NAND’s higher bit density and lower cost. To meet these criteria, several new technologies are being explored. Some are targeting embedded applications such as systems on chips (SoCs), while others are focused on the storage-class memory space.

Figure 1. DRAM/SRAM and flash have opposing characteristics that leave a gap to be filled by storage-class memory.

Two types already widely in use are magneto-resistive RAM (MRAM) for embedded memory applications and phase-change RAM (PCRAM) for storage-class memory: a single MRAM cell is found on the read heads of hard disk drives, and PCRAM is the technology underlying CDs and DVDs. However, neither of these applications requires cells that are dense enough to serve as standalone memory.

To manufacture these new devices as standalone memory, compatibility with current CMOS process technology is important for managing production costs. They include materials not typically used in standard CMOS production when embedded with other circuits. For MRAM, these atypical materials include Ru, Ta, and TiN for the electrodes; CoFe, NiFe, CoFeB, PtMn, IrMn, and Ru for the magnetic layer; and Al2O3, MgO, and NiO as the dielectric. PCRAM, meanwhile, uses chalcogenides – principally Ge2Sb2Te (GST) and InSbTe.

One challenge is that these materials can be damaged during the etch process. In existing applications, the cells are large enough such that the damage is inconsequential. However, for dense arrays of small cells, the challenges must be understood and overcome. Moving from reactive ion etch (RIE) to ion- beam etch (IBE) and implementing in-situ encapsulation are two techniques that can promote MRAM as embedded memory and PCRAM as storage-class memory.

Chemical Damage During RIE
Etch byproducts for more conventional CMOS materials are gaseous, making them easy to purge and remove from the etch reaction chamber. However, MRAM materials as described above tend to have non-volatile byproducts that can end up deposited all over the wafer, causing shorts and resulting in a tapered cell stack. Thus developing strategies for etching these materials is one of the key challenges to enabling their integration for memory applications.

Figure 2. Non-volatile MRAM etch byproducts are deposited across the wafer, causing a tapered MRAM cell stack.

An additional challenge is protecting the magnetic layer after the etch process. Some etch applications use halogen-based chemistries, which can corrode magnetic materials when exposed to air. A similar challenge exists for MgO dielectric layers: halogens – Chlorine and Fluorine – are again the culprits, causing damage that can compromise the performance of the cell.

RIE processes rely on chemical reactions on the wafer. In addition, ions are accelerated by a field between an electrode in the etch chamber and the wafer itself. Because the wafer functions as an electrode, ions always strike orthogonally (perpendicular) to the wafer plane.

With IBE, the etch mechanism is purely ion bombardment; it’s physical, not chemical, thereby eliminating chemical damage. In addition, the electric field is set up by independent electrodes, allowing the wafer to remain neutral. This means that the wafer can be tilted and rotated relative to the direction of the ions to ensure that the etch process can remove tapered sections of the stack.

Hydration and Oxidation Post-Etch
Yet another challenge is unwanted hydration of MgO and the oxidation of other layers after etching, but before the encapsulation that protects these materials. Oxygen and moisture in the ambient cause this contamination quickly – within seconds to hours. This results in closure of the programmed/erased window (Ron/Roff), making it harder to read the cell reliably. The chalcogenides used for PCRAM can similarly suffer from oxidation as they travel from the etch chamber to the encapsulation chamber. The solution here is to control the ambient and manage the interaction with the ambient after etch.

Figure 3. Oxygen and water can diffuse into the top layer prior to encapsulation, contaminating the chalcogenide material.

Etch Techniques for Next-Generation Memories
MRAM and PCRAM technologies are leading candidates in the race to establish storage-class memory that can supplement the use of DRAM, SRAM, and flash memory while performing well embedded in CMOS wafers. Shrinking and packing the cells to make them suitable for dense arrays requires changes to etch technologies.

Using IBE instead of RIE and implementing control the queue time and expose to ambient are two innovations that the industry, including Lam Research, is developing to spur the adoption of cost- effective, high-yielding memories in embedded applications.

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