Optimizing Your DRC Debug Can Reap Big Productivity Gains
By Srinivas Velivala - 10 May, 2018 - Comments: 0

Debugging design violations found by design rule checking (DRC) has always taken a significant share of the time needed to get a design to tapeout. And debug time only increases as the number and complexity of DRC expands with each new process node. Any steps you can take to make your DRC debug process more efficient directly improves your productivity. One technique for minimizing debug tim... » read more

Developing ASIL Ready SoCs For Self-Driving Cars
By Gordon Cooper - 10 May, 2018 - Comments: 0

Artificial intelligence (AI) and deep learning using neural networks is a powerful technique for enabling advanced driver-assistance systems (ADAS) and greater autonomy in vehicles. As AI research moves rapidly, designers are facing tough competition to provide efficient, flexible, and scalable silicon and software to handle deep learning automotive applications like inferencing in embedded vis... » read more

Power Optimization Strategies Widen
By Brian Bailey - 10 May, 2018 - Comments: 0

An increasing amount of electronic content in new and existing markets is creating different and sometimes competing demands for power optimization. For the past decade, EDA has been driven by the mobile phone industry, where the emphasis is on better power analysis and optimization tools to reduce power consumption and extend battery life. While energy efficiency continues to improve, other... » read more

Where The Rubber Hits The Road: Implementing Machine Learning On Silicon
By Dave Pursley - 10 May, 2018 - Comments: 0

Machine learning (ML) is everywhere these days. The common thread between advanced driver-assistance systems (ADAS) vision applications in our cars and the voice (and now facial) recognition applications in our phones is that ML algorithms are doing the heavy lifting, or more accurately, the inferencing. In fact, neural networks (NN) can even be used in application spaces such as file compressi... » read more

Tech Talk: HBM vs. GDDR6
By Ed Sperling - 10 May, 2018 - Comments: 0

Frank Ferro, senior director of product management at Rambus, talks about memory bottlenecks and why both GDDR6 and high-bandwidth memory are gaining steam and for which markets. https://youtu.be/CPqdZZooS2g     Related Video GDDR6 – HBM2 Tradeoffs (2019) What type of DRAM works best where. » read more

System-Level Power Modeling Takes Root
By Ann Mutschler - 10 May, 2018 - Comments: 0

Power, heat, and their combined effects on aging and reliability, are becoming increasingly critical variables in the design of chips that will be used across a variety of new and existing markets. As more processing moves to edge, where sensors are generating a tsunami of data, there are a number of factors that need to be considered in designs. On one side, power budgets need to reflect th... » read more

Tech Talk: Shrink Vs. Package
By Ed Sperling - 10 May, 2018 - Comments: 0

Andy Heinig, group manager for system integration at Fraunhofer EAS, talks about the tradeoffs between planar design and advanced packaging, including different types of interposers, chiplets and thermal issues. https://youtu.be/1BDqgCujJno » read more

The Future Of Mobile PC Is Here
By Sriram Ragunathan - 10 May, 2018 - Comments: 0

The smartphone has fundamentally changed the way other types of computing devices are being designed. Focus on energy-efficient compute, portable form factor, long battery life, and connectivity has spread far wider than just the smartphone in your hand. Nowhere has this design influence been more significant than in the area of notebook PC. The era we are just now entering is that of th... » read more

Does Power Verification Work?
By Brian Bailey - 10 May, 2018 - Comments: 1

Functional verification continues to evolve, but power verification—a somewhat new concern—remains at levels of sophistication reminiscent of functional verification 30 years ago. When will power verification catch up and what must to happen to make it possible? These are questions that the industry is still grappling with, and not everyone believes they require answers. Functional error... » read more

Implementation Of An Asynchronous Bundled-Data Router For A GALS NoC In The Context Of A VSoC
By Fraunhofer IIS/EAS - 09 May, 2018 - Comments: 0

Designs of asynchronous networks-on-chip are of growing interest because a complete asynchronous implemen- tation can solve the synchronization problems of large networks. However, asynchronous circuits suffer from the lack of proper design flows because their functionality often relies on timing constraints, which are not extensively supported by common CAD synthesis tools. This paper proposes... » read more

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