Cradle-To-Grave Analysis Of The Carbon Footprint of AI Hardware (Google)
By Technical Paper Link - 24 Feb, 2025 - Comments: 0

A new technical paper titled "Life-Cycle Emissions of AI Hardware: A Cradle-To-Grave Approach and Generational Trends" was published by researchers at Google. Abstract "Specialized hardware accelerators aid the rapid advancement of artificial intelligence (AI), and their efficiency impacts AI's environmental sustainability. This study presents the first publication of a comprehensive AI acc... » read more

Linear Pluggable Optics Save Energy In Data Centers
By Bryon Moyer - 24 Feb, 2025 - Comments: 0

Linear pluggable optics (LPO) is garnering more attention as a way to quickly and efficiently move data in and out of server racks, but a lack of standards for connecting the optical modules is slowing adoption at a time when there is growing pressure to reduce power in data centers. LPO is the newest of two approaches to solving the power wall problem in data centers. Co-packaged optics (CP... » read more

Chip Industry Week In Review
By The SE Staff - 21 Feb, 2025 - Comments: 0

The EU Commission approved €920 million in German State aid to support Infineon in setting up its Smart Power Fab in Dresden. Total funding for the Dresden site amounts to about €1 billion. PDF Solutions will acquire secureWISE for $130 million to expand the reach of its semiconductor manufacturing data platform, providing secure, remote access monitoring and control. Tariffs, trade, and ... » read more

Low-Cost TSV Repair Architecture Specialized for Highly Clustered TSV Faults Within HBM
By Technical Paper Link - 20 Feb, 2025 - Comments: 0

A new technical paper titled "Low Cost TSV Repair Architecture Using Switch-Based Matrix for Highly Clustered Faults" was published by researchers at Yonsei University. Abstract "Through-silicon via (TSV), responsible for inter-layer communication in high-bandwidth memory (HBM), plays a critical role in HBM operation. Therefore, faults occur in TSVs can critically impact the entire chips. H... » read more

Back-End Packaging And Test: From Lessons Learned To Future Innovations
By Jessica Albright - 20 Feb, 2025 - Comments: 0

The semiconductor industry is a hallmark of technological innovation, evolving rapidly to meet the demands of an increasingly digital world. At its core, semiconductor manufacturing involves two main stages: front-end processes, (wafer fabrication) and back-end processes (packaging and test). Wafer fabrication consists of creating microscopic electronic circuits on a silicon wafer. Packaging an... » read more

Energy Saving In Semiconductor Packaging Plating Processes Through Chemical Deflashing Process Optimization
By Arieff Yusoff - 20 Feb, 2025 - Comments: 0

In response to the rising focus on sustainable manufacturing practices and corporate social responsibility, there has been a surge of interest in adopting environmentally friendly and green chemicals for semiconductor manufacturing processes. These alternatives aim to minimize hazards while promoting greater sustainability. Notably, this trend extends to exploring substitutes for conventional c... » read more

Speeding Up Computational Lithography With The Power And Parallelism Of GPUs
By Thuc Dam - 20 Feb, 2025 - Comments: 0

There are so many challenges in producing modern semiconductor devices that it’s amazing for the industry to pull it off at all. From the underlying physics to fabrication processes to the development flow, there is no shortage of tough issues to address. Some of the biggest arise in lithography for deep submicron chips. A recent post outlined the major trends in lithography and summarized a ... » read more

Advanced Packaging Evolution: Chiplet And Silicon Photonics-CPO
By Vincent Lin - 20 Feb, 2025 - Comments: 0

As we enter the AI era, the demand for enhanced connectivity in cloud services and AI computing continues to surge. With Moore’s Law slowing down, the increasing data rate requirements are surpassing the advancements of any single semiconductor technology. This shift underscores the importance of heterogeneous integration (HI) as a crucial solution for alleviating bandwidth bottlenecks. Tod... » read more

Interconnects Approach Tipping Point
By Laura Peters - 20 Feb, 2025 - Comments: 0

As leading devices move to next generation nanosheets for logic, their interconnections are getting squeezed past the point where they can deliver low resistance pathways. The 1nm (10Å) node will have 20nm pitch and larger metal lines, but the interconnect stack already consumes a third of device power and accounts for 75% of the chip's RC delay. Changing this dynamic requires a superior co... » read more

Mechanical Stress In Semiconductor Development
By Ivan Chakarov - 20 Feb, 2025 - Comments: 0

With the semiconductor industry moving toward 3D DRAM, 3D logic architectures, and 1000+ layer 3D NAND stacks,1 mechanical failures may become more common. Due to the complexity of these structures, mechanical stress from materials processing has the potential to significantly impact yield. 3D processing techniques (etching, deposition, and related chemistries), as well as material property de... » read more

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