Reimagine Enterprise Data Center Design and Operations


The Power of Digital Twin Technology This eBook showcases how large enterprises across various industries, such as aerospace, healthcare, automotive and financial services, use digital twin software to overcome unique challenges, resulting in: 30-40% reduction in power consumption and increased efficiency Extended data center lifespan and resisted cloud migration pressures Impro... » read more

Software-Defined Vehicles for Dummies


This latest Dummies Guide takes you through the captivating world of software-defined vehicles (SDVs), offering important insights into the technologies and systems that propel SDVs, and their impact on the future of transportation. This book covers the foundational understanding of SDVs and progressively delves into their various aspects, exploring the potential implications of this rapidly ev... » read more

Striking A Balance On Efficiency, Performance, And Cost


Experts at the Table: Semiconductor Engineering sat down to discuss power-related issues such as voltage droop, application-specific processing elements, the impact of physical effects in advanced packaging, and the benefits of backside power delivery, with Hans Yeager, senior principal engineer, architecture, at Tenstorrent; Joe Davis, senior director for Calibre interfaces and EM/IR product m... » read more

Steps to Fabricate Nanotips Overhanging From Chip Edge By a Few Micrometers (CNRS, CEA-Leti)


A new technical paper titled "Suspended tip overhanging from chip edge for atomic force microscopy with an optomechanical resonator" was published by researchers at Lab. d'Analyse et d'Architecture des Systèmes du CNRS and CEA-LETI. Abstract Raising the mechanical frequency of atomic force microscopy (AFM) probes to increase the measurement bandwidth has been a long-standing expectation in... » read more

Hardware-Side-Channel Leakage Contracts That Account For Glitches and Transitions (TU Graz)


A new technical paper titled "Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches" was published by researchers at Graz University of Technology. Abstract "Security verification of masked software implementations of cryptographic algorithms must account for microarchitectural side-effects of CPUs. Leakage contracts were proposed to provide a formal separation bet... » read more

Analog In-Memory Computing: Fast Deep NN Training (IBM Research)


A new technical paper titled "Fast and robust analog in-memory deep neural network training" was published by researchers at IBM Research. Abstract "Analog in-memory computing is a promising future technology for efficiently accelerating deep learning networks. While using in-memory computing to accelerate the inference phase has been studied extensively, accelerating the training phase has... » read more

Taking Data Center Serviceability To The Next Level


It is no secret that Artificial Intelligence (AI) workloads are driving an exponential growth in the scale of supercomputers and data centers. Training the latest LLM (Large Language Model), for instance, typically requires thousands of specialized processing cores running at full speed. As these models get more advanced with each generation, they need additional compute performance to absorb a... » read more

Defect Challenges Grow At The Wafer Edge


Reducing defects on the wafer edge, bevel, and backside is becoming essential as the complexity of developing leading-edge chips continue to increase, and where a single flaw can have costly repercussions that span multiple processes and multi-chip packages. This is made more difficult by the widespread rollout of such processes as hybrid bonding, which require pristine surfaces, and the gro... » read more

How The Semiconductor Ecosystem Is Responding To Its Global Challenges


The semiconductor industry is changing rapidly, with government support for re-shoring capacity creating new interplay among resources in Asia, the U.S., and Europe—even as the industry develops and sustains new technologies like HBM and heterogeneous integration. Geopolitical factors such as the CHIPS (Creating Helpful Incentives to Produce Semiconductors for America) Act, the scarcity of s... » read more

Promises and Perils of Parallel Test


Testing multiple devices at the same time is not providing the equivalent reduction in overall test time due to a combination of test execution issues, the complexity of the devices being tested, and the complex tradeoffs required for parallelism. Parallel testing is now the norm — from full wafer probe DRAM testing with thousands of dies to two-site testing for complex, high-performance c... » read more

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