What’s Next For Emulation
By Brian Bailey - 28 Oct, 2021 - Comments: 1

Emulation is now the cornerstone of verification for advanced chip designs, but how emulation will evolve to meet future demands involving increasingly dense, complex, and heterogeneous architectures isn't entirely clear. EDA companies have been investing heavily in emulation, increasing capacity, boosting performance, and adding new capabilities. Now the big question is how else they can le... » read more

Functional Safety Across Analog And Digital Domains
By Frank Schirrmeister - 28 Oct, 2021 - Comments: 1

The autonomy of vehicles has been all the rage recently. There are different levels of autonomous driving, with level 5 “Full Automation” being the target the industry is working towards, and Level 2 “Partial Automation” and Level 3 “Conditional Automation” being the level at which the automotive sector currently delivers the most technology. The amount of electronics in cars has be... » read more

Partitioning For Better Performance And Power
By Ann Mutschler - 28 Oct, 2021 - Comments: 0

Partitioning is becoming more critical and much more complex as design teams balance different ways to optimize performance and power, shifting their focus from a single chip to a package or system involving multiple chips with very specific tasks. Approaches to design partitioning have changed over the years, most recently because processor clock speeds have hit a wall while the amount of d... » read more

High-Level Synthesis For RISC-V
By Brian Bailey - 28 Oct, 2021 - Comments: 2

High-quality RISC-V implementations are becoming more numerous, but it is the extensibility of the architecture that is driving a lot of design activity. The challenge is designing and implementing custom processors without having to re-implement them every time at the register transfer level (RTL). There are two types of high-level synthesis (HLS) that need to be considered. The first is ge... » read more

Debug Solutions For Designers Accelerate Time To Verification
By Neil Hand - 28 Oct, 2021 - Comments: 0

Complexity continues to explode as designs become larger and more complicated with more functionality and more aggressive expectations. The cost of doing business as usual, for the entire design and verification team, in turn, grows exponentially, in terms of time, effort, and dollars. Fig. 1: Discovering issues later than possible requires more effort to find and fix. (Source: Wilson Rese... » read more

Intelligent Coverage Optimization: Verification Closure In Hyperdrive
By Anika Malhotra - 28 Oct, 2021 - Comments: 0

Coverage dominates every aspect of verification for today’s complex IP and chip designs. Coverage metrics provide critical feedback on what has been verified and what has not, especially when automated stimulus generation techniques are used. All modern hardware design and verification languages include constructs for functional coverage specification and support a range of structural coverag... » read more

Customize Off-The-Shelf Processor IP
By Roddy Urquhart - 28 Oct, 2021 - Comments: 0

Processor customization is one approach to optimizing a processor IP core to handle a certain workload. In some case it makes sense to design a dedicated core from scratch, but in many cases an existing core may partially meet your requirements and can be a good starting point for your optimized core. In the past some processor IP vendors, notably ARC and Tensilica, offered extensible cores ... » read more

Materials and Device Simulations for Silicon Qubit Design and Optimization
By Technical Paper Link - 27 Oct, 2021 - Comments: 0

Abstract: "Silicon-based microelectronics technology is extremely mature, yet this profoundly important material is now also poised to become a foundation for quantum information processing technologies. In this article, we review the properties of silicon that have made it the material of choice for semiconductor-based qubits with an emphasis on the role that modeling and simulation have play... » read more

Buried nanomagnet realizing high-speed/low-variability silicon spin qubits: implementable in error-correctable large-scale quantum computers
By Technical Paper Link - 27 Oct, 2021 - Comments: 0

Abstract: "We propose a buried nanomagnet (BNM) realizing highspeed/low-variability silicon spin qubit operation, inspired by buried wiring technology, for the first time. High-speed quantum-gate operation results from large slanting magnetic-field generated by the BNM disposed quite close to a spin qubit, and low-variation of fidelity thanks to the self-aligned fabrication process. Employing ... » read more

3D Printing For More Circuits
By Ann R. Thryft - 27 Oct, 2021 - Comments: 0

After several years of experimentation, and growing success in volume manufacturing for some use cases, technologies for 3D printing of electronic circuits are becoming more common. Some innovations in processes and materials are moving these technologies closer to mainstream electronics manufacturing. Christopher Tuck, professor of material science at the University of Nottingham, observed ... » read more

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