Boost For Verification Methodologies

By Ed Sperling

Synopsys introduced enhancements to its Verification Methodology Manual and Cadence began detailing new enhancements in its Open Verification Methodology. Both programs are in beta, yet they offer steps forward toward easing one of the biggest problem areas in chip development.

With verification still consuming 70% or more of the non-recurring engineering costs of semiconductor development, it’s no wonder that resources continue to pour into fixing this portion of the design cycle.

What’s changed?

VMM 1.2 is the follow-on to an update of this verification methodology originally created by Synopsys and ARM. In 2008, the first major extension pushed beyond the base class with an abstraction layer, a VMM planner, and the libraries were opened up to the open source community. This year, the methodology has been extended into the low-power domain, with base libraries, multi-voltage designs—work done jointly by Synopsys, ARM and Renesas.

The methodology includes three main categories of base classes, according to Tom Borgstrom, director of solutions marketing at Synopsys. First is SystemC, System Verilog and TLM 2.0 support. “Channel communications are easier if you come from SystemC TLM into System Verilog,” said Borgstrom.

The TLM 2.0 support adds remote procedure call functionality between components. There also is enhanced block-to-top re-use with hierarchical phasing. In addition, there is better ease of use with implicit phasing, paramaterization, the ability to control testbench functionality from the runtime command line, and a common base class.

OVM, meanwhile, was created by Mentor and Cadence, based largely on Cadence’s Incisive Plan-to-Closure Methodology as a way to provide a testbench methodology and class libraries so that verification environments could be scalable and re-usable. In Cadence’s case, it was integrated tightly with Specman, which is why the new Specman 9.2 beta includes an OVM scoreboard infrastructure package and more fine-grained access to various steps.

Both OVM and VMM see this fine-grained tuning as critical to future designs.

OVM 2.0.2 was released on June 18, as well, by Mentor and Cadence, including bug fixes and in-source documentation using NaturalDocs.

What engineers are (not) saying

But the fact that two rival methodologies continue to exist at the same time, spearheaded by rival companies, continues to raise eyebrows among design engineers.

Standards groups such as Accellera have done much to improve interoperability between these methodologies, and both sides have offered interoperability. Nevertheless, the continued independent development means there will be constant need for improvements in interoperability, as well.

The best insight into these worlds may come from the blogosphere, which is remarkably sparse for any technology as detailed as verification methodology. There is almost no crossover in the blogs between OVM and VMM, meaning engineers will continue using one language or the other even though other members of their dispersed teams may prefer something else. And while interoperability is possible, it’s difficult to discern whether it’s actually happening.