A look at automation capabilities that make physical prototyping a low risk in almost any ASIC design validation and software development task.
FPGA-based prototyping is so popular because it provides an economical way to functionally validate an ASIC design by creating a prototype that runs “at speed”, includes real world I/O, and enables early software development. Experienced prototypers are familiar with its benefits but there are still designers opposed to physical prototyping because they believe that it does not scale to support large capacity designs, prototype development takes too long, and once they have a working prototype, it’s too hard to debug. These are all myths rooted in the struggles of developing in-house prototypes with limited automation software of years past. This white paper busts these myths by showing automation capabilities that make physical prototyping a low risk for almost any ASIC design validation and software development task.
To read more, click http://www.synopsys.com/cgi-bin/proto/pdfdla/pdfr1.cgi?file=physical_proto_wp.pdf.
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