category: A Bit About Memory

category: IoT, Security & Automotive

Memory Buffer Chips: Satisfying Amdahl’s Law To Sustain Moore’s Law
By John Eble - 13 Jul, 2017 - Comments: 0

Moore’s Law, the observation that the available transistors in an integrated circuit doubles every two years, has driven the semiconductor and IT industries to unparalleled growth over the last 50+ years. These transistors have been used in CPUs to increase the number of parallel execution units and instruction fetches, expand the levels of on-chip cache (and overall capacity), support spe... » read more

From SerDes Chiplets To Die-To-Die Interfaces
By Mohit Gupta - 08 Jun, 2017 - Comments: 0

The demand for ever faster high-speed interfaces has never been quite so pronounced. In our increasingly connected world, petabytes of data are continuously generated by a wide range of devices, systems and IoT endpoints such as vehicles, wearables, smartphones and even appliances. The resulting digital tsunami has prompted industry heavyweights like Google, Microsoft, Facebook and Amazon to co... » read more

The SerDes – Terabit Ethernet Connection
By Mohit Gupta - 11 May, 2017 - Comments: 0

400 Gigabit Ethernet (400GbE) and 200 Gigabit Ethernet (200GbE) are currently slated for official release by the IEEE P802.3cd Task Force in December 2017. Although there is not yet an official IEEE roadmap detailing what lies beyond 400GbE, doubling to 800GbE will likely become a reality when single-lane 112Gbps links hits the market. This technology will allow for larger lane bundles, providi... » read more

Understanding SerDes Signal Integrity Challenges
By Bill Fuller - 13 Apr, 2017 - Comments: 0

Signal integrity (SI) can perhaps best be defined as a set of measures of the quality of electrical signals, which are subject to the effects of noise, distortion and loss. Additional signal integrity issues include jitter, ringing, crosstalk, ground bounce and power supply noise. There are multiple factors that can negatively influence signal integrity, thereby causing errors and system fai... » read more

HBM2: It’s All About The PHY
By Bill Fuller - 09 Mar, 2017 - Comments: 0

HBM DRAM is currently used in graphics, high-performance computing (HPC), server, networking and client applications. HBM, says JEDEC HBM Task Group Chairman Barry Wagner, provides a “compelling solution” to reduce the IO power and memory footprint for the most demanding applications. Recent examples of second-generation HBM deployment include NVIDIA’s Quadro GP100 GPU which is paired wit... » read more

The Challenges Of Designing An HBM2 PHY
By Frank Ferro - 09 Feb, 2017 - Comments: 1

Originally targeted at the graphics industry, HBM continues to gain momentum in the server and networking markets as system designers work to move higher bandwidth closer to the CPU. Expanding DRAM capacity – which boosts overall system performance – allows data centers to maximize local DRAM storage for wide throughput. HBM DRAM architecture effectively increases system memory bandwidth... » read more

The Challenges Of Designing 28G And 56G SerDes IP
By Jeff Kaady - 12 Jan, 2017 - Comments: 1

The industry move to 56 Gbps PAM4 is undoubtedly one of the greatest challenges currently facing SerDes IP designers and their customers. To begin with, shifting to 56 Gbps PAM4 immediately causes a loss of 9 dB. While the baud rate is 28 Gbaud, there are now three eyes stacked on top of each other. Nevertheless, there is still demand for 35+ dB reach. This is a significant challenge which requ... » read more

What Comes After Moore’s Law And Dennard Scaling?
By Steven Woo - 08 Dec, 2016 - Comments: 0

For decades, Moore’s Law has been an important semiconductor industry mainstay that has helped fuel a relentless progression in computing performance. However, most industry experts agree that Moore’s Law is waning, with an end on the horizon due to a combination of physical limitations and economic factors. With the loss of Dennard Scaling roughly 10 years ago, the industry is at a critica... » read more

Faster SerDes For More Efficient Data Centers
By Steven Woo - 10 Nov, 2016 - Comments: 0

The evolving data center presents an imposing set of challenges for system architects as Dennard Scaling fades and Moore’s Law wanes. These include an exponential increase in data, shifting architectural bottlenecks and a never-ending demand for higher performance within the same power and thermal envelopes. The Internet of Things (IoT), Big Data analytics, in-memory computing and machine ... » read more

From The Data Center To The Mobile Edge
By Steven Woo - 13 Oct, 2016 - Comments: 0

At the heart of the Internet of Things is the complex interplay between the needs for both low power and high performance (LPHP), a perplexing challenge rooted in the de-facto bifurcation of the IoT itself. For example, lower power mobile devices, systems and lite endpoints make up the vast majority of forward-facing consumer infrastructure, while high-performance servers at the back end are ta... » read more

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