Low Power Simulation


By Luke Lang Once in a while I’m asked if it’s necessary to check power and ground connections with VDD/VSS-aware simulation on a physical (PG) netlist. The short answer is: “No, as long as you have run LP structural verification. But if it will help you sleep better at night, then go for it.” For the longer answer, keep reading. In order to run VDD/VSS-aware simulation, one must ha... » read more

The Real Value Of An LP Methodology


By Luke Lang “What are some of the low-power mistakes that you have seen?” That is, by far, the most popular question asked by designers. And it’s a very good question. Why re-invent the wheel? Why repeat mistakes? It’s a lot easier to learn from someone else’s mistakes than from your own. Clearly, every company is different, and every design is different. But there are lots of co... » read more

RTL Power Estimation


By Luke Lang A few months ago, I wrote about power estimation—finding the worst-case toggle rate to determine the worst-case power. This has been used very successfully by many designers to get an accurate estimation and analysis of power dissipation. These designers also are using the worst-case toggle rate to optimize power grid and meet dynamic IR drop requirements. With these power estim... » read more

Fast LP Simulation


By Luke Lang What are the most important features of a logic simulator? I’m sure there have been lots of surveys done for this question. Unfortunately, I can’t find any results on Google. Nevertheless, I would be willing to bet that fast performance is at or near the top of every verification engineer’s wish list. For the low-power verification engineers, fast performance is also a ke... » read more

Golden Power Intent


By Luke Lang A few months ago, I wrote about the rapid adoption of the power intent file for low-power designs. While this is certainly a step in the right direction, some design teams may be taking several steps backwards by not treating the power intent file with the proper respect. For example, I have seen one case where the verification, synthesis, and backend implementation teams each had... » read more

What’s Your Toggle Rate?


By Luke Lang Now that power is a key specification, designers are looking into various design techniques to reduce power. One thing that designers realize very quickly is that there is a cost associated with these low-power techniques. Some of these costs are silicon area and design complexity. Very quickly, designers face the tradeoff of cost vs. power saving. In order to analyze this tradeof... » read more

Power Intent Files Drive Low Power Adoption


By Luke Lang “The adoption of EDA tools is actually a very slow process.” This quote by Wally Rhines of Mentor Graphics was highlighted in a red box in the June 2010 issue of EDA Tech Forum. I don’t think most of us would argue with that statement. But there are certainly exceptions to that rule, and low-power design with a power-intent file is one such exception. The concept of a pow... » read more

Structural Verification Finds Mixed-Signal LP Errors


By Luke Lang In the last blog, I gave some reasons why there is no low power (LP) analog/mixed-signal solution. However, this does not mean there is no effort in this area. Toward the end of 2009 and early 2010, I worked with a customer to establish a LP analog/mixed-signal structural verification flow. This flow was proven to be extremely helpful. It caught several LP bugs that were not found... » read more

Why Low-Power Analog Solutions Are Lacking


By Luke Lang The need for low-power design has been well documented. The demand for low-power design solutions is at an all-time high. Just take a quick glance through the 2010 Design Automation Conference advanced program, and you’ll see that the word “low-power” appears repeatedly. These are exciting times for anyone associated with low-power design. Recent developments in low-power... » read more

Newer posts →