Comparison Of State-Of-The-Art Models For Socket Pin Defect Detection


This article is adapted from a presentation at TestConX, March 5-8, 2023, Mesa, AZ, by Vijayakumar Thangamariappan, Nidhi Agrawal, Jason Kim, Constantinos Xanthopoulos, Ira Leventhal, and Ken Butler, Advantest America Inc., and Joe Xiao, Essai, Advantest Group. Test sockets have a key role to play in the semiconductor test industry. A socket serves as the critical interface between a teste... » read more

MMAF Option Enables Picoampere Measurements


By Yoshiyuki Aoki and Tsunetaka Akutagawa Demand for low-current devices is increasing, as many new sensors are being created for medical, automotive, industrial, and other applications. Chief among the heightened production and test requirements for these low-current devices is the need to achieve picoampere (pA)-class measurements. Sensors’ functionality and efficacy, especially in medic... » read more

Design Considerations For Ultra-High Current Power Delivery Networks


This article is adapted from a presentation at TestConX, March 5-8, 2023, Mesa, AZ. A power-delivery network (PDN), also called a power-distribution network, is a localized network that delivers power from voltage-regulator modules (VRMs) throughout a load board to the package’s chip pads or wafer’s die pads. The PDN includes the VRM itself, all bulk and localized capacitance, board vi... » read more

Power-Supply Card Targets High-Voltage PMIC Test


The electronics industry is seeing a move toward higher voltages and currents to deliver sufficient supply and charging power in products ranging from handheld cellphones and tablets to workstations. This trend is evidenced in examples such as the many USB power-delivery (PD) profiles with ratings ranging from 10W (5V at 2A for USB PD 3.0 profile 1) up to 100W (5V at 2A, 12V at 5A, and 20V at 5... » read more

Data Analytics For The Chiplet Era


This article is based on a paper presented at SEMICON Japan 2022. Moore’s Law has provided the semiconductor industry’s marching orders for device advancement over the past five decades. Chipmakers were successful in continually finding ways to shrink the transistor, which enabled fitting more circuits into a smaller space while keeping costs down. Today, however, Moore’s Law is slowin... » read more

Device Validation: The Ultimate Test Frontier


This article is a condensed version of an article that appeared in the November/December 2022 issue of Chip Scale Review. Adapted with permission. Read the original article at https://chipscalereview.com/wp-content/uploads/flipbook/30/book.html, p. 26. In the early days of space exploration, spacecraft were manned by small teams of astronauts, most of whom were experienced test pilots who ... » read more

Test Gets Ready For Wi-Fi 7


New test solutions are emerging to address the test challenges associated with the forthcoming Wi-Fi 7 standard. Wi-Fi 7 covers the (so far, for Wi-Fi) unused frequency range between 6 GHz and 7.125 GHz, using up to 4096-QAM modulation schemes and up to 320MHz channel bandwidth (see figure 1). Fig. 1: Wi-Fi band ranges are shown here, including the 3x increase in bandwidth enabled by a... » read more

Engineering Test Station Facilitates Post-Silicon Validation


The semiconductor market is evolving, with devices becoming more complex as chip designers add cores and pursue 2.5D and 3D integration strategies. This complexity presents challenges extending from design and simulation through system-level test (SLT), where a device is exercised in mission mode, booting up an operating system and running end-user code, for example. These challenges arise f... » read more

Industrial Solutions For Machine-Learning-Enabled Yield Optimization And Test


This article summarizes the content of a paper developed and presented by Advantest at ETS 2022. By Sonny Banwari and Matthias Sauer According to market research firm Gartner, Inc., in assessing the completion rate of data science projects, as well as the bottom-line value they generate for their companies, only between 15 and 20 percent of these projects are ever completed. Moreover, of ... » read more

A Customized Low-Cost Approach For S-Parameter Validation Of ATE Test Fixtures


This article summarizes the content of a paper jointly developed and presented by Advantest and Infineon at TestConX 2022. Device under test (DUT) fixtures for ATE systems pose several verification challenges. Users need to measure the DUT test fixture quickly and easily, while making sure the measurements mimic the ATE-to-test-fixture interface performance and determining how to handle DUT ... » read more

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