Corner-Case Bug Hunting for RISC-V

By Ashish Darbari - 30 Sep, 2024 - Comments: 0

By Ashish Darbari and Ia Tsomaia RISC-V continues to make headlines worldwide, but verification continues to be challenging. The findings of the Wilson Research Report, 2022 (see figure 1) make the trends in verification clear. We presented these in a keynote talk titled, "Future is Formal," at the recent DVCon India event. One thing is quite apparent: whether you are using directed tests... » read more

Insights From The AI Hardware & Edge AI Summit

By Ashish Darbari - 25 Jul, 2024 - Comments: 0

By Ashish Darbari, Fabiana Muto, and Nicky Khodadad In today's rapidly changing technology landscape, artificial intelligence (AI) is more than a buzzword. It is transforming businesses and societies. From advances in scalable AI methodology to urgent calls for sustainability, the AI Hardware & Edge AI Summit recently held in London, sparked vibrant discussions that will determine the fu... » read more

RISC-V Verification: From Simulation To Formal

By Ashish Darbari - 27 Jun, 2024 - Comments: 0

Axiomise's Nicky Khodadad and Ashish Darbari discuss simulation and the need for formal verification and RISC-V, including why simulation-based verification is inadequate to find all the bugs in a design and how formal verification can help with bug hunting for corner-case bugs and exhaustive proofs of bug absence. » read more

Verification In Crisis

By Ashish Darbari - 25 Apr, 2024 - Comments: 0

Why is it still so hard to ensure good quality sign-off happens without leaving behind bugs in silicon? The answer, according to my colleagues at DVCon, is highly nuanced. The industry has been improving overall, as has the complexity of designs. For ASICs, 74% of the designs surveyed in the recent Wilson Research Group/Siemens EDA report have one or more processor cores, 52% have two or mor... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

category: Making Formal Normal

category: IoT, Security & Automotive

Corner-Case Bug Hunting for RISC-V

Insights From The AI Hardware & Edge AI Summit

RISC-V Verification: From Simulation To Formal

Verification In Crisis