Challenges In Using HLS For FPGA Design


High-level synthesis (HLS) tools, which transform C/C++ source code to Verilog/VHDL, have been commercially available for over 15 years. HLS tools from FPGA vendors and EDA companies promise improved productivity through a higher-level of abstraction, faster verification and quicker design iterations. For example, simulating your design in C/C++ can be 10 to 100x faster than simulating in RTL (... » read more

Finding And Avoiding Concurrency Bugs


Understanding the intended and unintended interactions between hardware and software components is changing as architectures become more heterogeneous and interconnect topologies get more complicated. This affects performance, power consumption and cost of the project. Lots of universities are researching this from a software perspective, while a small number are looking at the implications fro... » read more

Getting A Complete Picture Of Automotive Software


The automotive industry is currently undergoing a major disruption, usually referred as the shift to automated, connected, electric, and shared vehicles (ACES[1]). Naturally, these changes also have a significant impact on the requirements of the hard- and software architectures of these new vehicles: Service-oriented software architectures used by multiple applications running on generali... » read more

Inaccurate Assumptions Mean Software Issues


It doesn’t seem that long ago when features and functionality were being added to next generation processors and SoCs ahead of demand. Actually, I recall when new processors were released, embedded software developers were forced to think of innovative ways to exploit the new features in order to differentiate the product to not be left behind. Today, in many respects it seems as if the... » read more