The New Face of Formal


Semiconductor engineering sat down to discuss the recent growth in adoption of formal technologies and tools with Lawrence Loh, product engineering group director at [getentity id="22032" e_name="Cadence"], Praveen Tiwari, senior manager R&D, verification group at [getentity id="22035" e_name="Synopsys"], Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"], Normando... » read more

The New Face Of Formal


Semiconductor Engineering sat down to discuss the recent growth in adoption of formal technologies and tools with Lawrence Loh, product engineering group director at [getentity id="22032" e_name="Cadence"], Praveen Tiwari, senior manager of R&D in the verification group at [getentity id="22035" e_name="Synopsys"], Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphic... » read more

Making Hardware Design More Agile


Semiconductor engineering sat down to whether changes are needed in hardware design methodology, with Philip Gutierrez, ASIC/FPGA design manager in [getentity id="22306" comment="IBM"]'s FlashSystems Storage Group; Dennis Brophy, director of strategic business development at [getentity id="22017" e_name="Mentor Graphics"]; Frank Schirrmeister, group director for product marketing of the System ... » read more

Making Hardware Design More Agile


Semiconductor engineering sat down to whether changes are needed in hardware design methodology, with Philip Gutierrez, ASIC/FPGA design manager in [getentity id="22306" comment="IBM"]'s FlashSystems Storage Group; Dennis Brophy, director of strategic business development at [getentity id="22017" e_name="Mentor Graphics"]; Frank Schirrmeister, group director for product marketing of the System ... » read more

The Future Of Moore’s Law


Semiconductor Engineering sat down to discuss the future of Moore's Law with Jan Rabaey, Donald O. Pederson distinguished professor at [getentity id="22165" comment="UC Berkeley"]; Lucio Lanza, managing director of Lanza techVentures; Subramani Kengeri, vice president of advanced technology architecture at [getentity id="22819" comment="GlobalFoundries"]; Charlie Cheng, CEO of [getentity id="2... » read more

Making Hardware Design More Agile


Semiconductor engineering sat down to whether changes are needed in hardware design methodology, with Philip Gutierrez, ASIC/FPGA design manager in [getentity id="22306" comment="IBM"]'s FlashSystems Storage Group; Dennis Brophy, director of strategic business development at [getentity id="22017" e_name="Mentor Graphics"]; Frank Schirrmeister, group director for product marketing of the System ... » read more

The Future Of Moore’s Law


Semiconductor Engineering sat down to discuss the future of Moore's Law with Jan Rabaey, Donald O. Pederson distinguished professor at [getentity id="22165" comment="UC Berkeley"]; Lucio Lanza, managing director of Lanza techVentures; Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries; Charlie Cheng, CEO of [getentity id="22135" e_name="Kilopass Technology"... » read more

The Future Of Moore’s Law


Semiconductor Engineering sat down to discuss the future of Moore's Law with Jan Rabaey, Donald O. Pederson distinguished professor at [getentity id="22165" comment="UC Berkeley"]; Lucio Lanza, managing director of Lanza techVentures; Subramani Kengeri, vice president of advanced technology architecture at [getentity id="22819" comment="GlobalFoundries"]; Charlie Cheng, CEO of [getentity id="2... » read more

Full Coverage Or Full Monty


Without adequate coverage metrics and tools, verification engineers would never be able to answer the proverbial question: are we done yet? But a lot has changed in the design flow since the existing set of metrics was defined. Does it still ensure that the right things get verified, that time is not wasted on things deemed unimportant or a duplication of effort, and can it handle today’s hie... » read more

Full Coverage Or Full Monty?


Without adequate coverage metrics and tools, verification engineers would never be able to answer the proverbial question: are we done yet? But a lot has changed in the design flow since the existing set of metrics was defined. Does it still ensure that the right things get verified, that time is not wasted on things deemed unimportant or a duplication of effort, and can it handle today’s hie... » read more

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