Challenges In Creating Power-Managed IP

Can power-managed IP can be created without working closely with the chip vendor?

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By Bhanu Kapoor
Creating low power IPs worked fairly well—at least until the process technology nodes for which leakage power wasn’t a big issue and clock gating was able to address dynamic power optimization. For 90nm and more advanced process technology nodes, leakage power became a dominant issue and the dynamic power needed better optimization. The use of voltage-based power management techniques such as adaptive voltage scaling, dynamic power switching, standby leakage management, forward and reverse body biasing, and state retention required changing voltages, and that tied power management closely to the process technologies.

ARM is known to have worked closely with companies such as Texas Instruments and QualComm over the years to create processor IPs that are used in application platforms such as OMAP and Snapdragon. The power-management techniques used are process-node dependent (such as versions of TSMC’s 65nm and 40nm nodes), and require application platforms support for various techniques. For example, ARM provides two hard IP cores for its Cortex-A9 processor. One targets high-performance applications and the other targets low-power applications.

It is not clear if an IP provider can effectively provide a soft IP along with power specification written in IEEE p1801 format and hand it over to the SoC vendor as a soft power-managed IP. There are many more challenges to enabling this kind of handoff in addition to some mentioned above such as:

  1. A power-managed IP has to work closely with system’s power controller unit and appropriate considerations must be taken into account. This is further complicated in situations where the platform creator also ties power management ICs to the platform.
  2. Power management cells within the IP, such as isolation cells, level-shifters, power switches, and isolating level-shifters, are process-technology dependent. Any analog circuit has to be re-created for each process technology node.
  3. If your technique ties you to other components on the SoC such as a state-retention technique utilizing RAM, then that is another application platform dependence you have to take into account.
  4. If the IP itself has complex power management in place, then its validation in the system context truly can only happen at the system-level—and at times only using the system software.

All of these issues make creation of a power-managed IP a challenging task, and it is not clear if a complex power-managed IP can be created without working closely with the full-chip vendor. For IP vendors, this further points to services becoming even more integral part of IP selling process in future.

–Bhanu Kapoor is the founder and president of Mimasic, a low-power consultancy.


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