Chip-Package-Board Optimization: The Future Of Integrated Co-Design

As complexity grows, trying to figure this out on a spreadsheet is a monumental task that is prone to error.


Multi-die and three-dimensional packages have made breakout and routing of extremely high-pin-count devices on PCBs very difficult. Keeping track of all the signals and pins is also a task that has just about outgrown current methods. Many companies simply use a spreadsheet for tracking signals. With no central database or accurate device modeling and rule-based optimization, design intent is often misinterpreted or lost. Spreadsheets also introduce the strong possibility of error.

Figure 1: This enormous spreadsheet is typical of signal/pin tracking commonly used today.

The ideal flow would include several key pieces of functionality in a formal co-design flow that supports the requirements of the IC, package substrate and printed circuit board designer, while introducing the concept of targeting multiple potential board level platforms. Let’s briefly explore the “why” as well as the “how”.

Multiple Products for One Chipset
Not infrequently, the same chipset is used for multiple products. For example, it might be targeted at both a smart phone and tablet form factor. Each platform likely would have unique mechanical, thermal and electrical requirements. Determining the best package for each product is a significant challenge.

Suppose a processor needs to work with memory devices provided by multiple vendors, each with their own pin-out. Determining the ideal pin-out for the processor package should be coordinated with routing studies at the board level. What if minor adjustments to the pin pitch on your package could lead to a more routable PCB, thus reducing the total number of routing layers?

Today, these questions are answered with the spreadsheet methods and white board discussions that are prone to human error and can lead to redundancy, while providing very little design automation.

Planning and Optimization
Planning and optimization is critical for the best possible package and pinout determination. What is needed is an integrated platform that models the floor-plan and I/O requirements of the IC, along with the package substrate constraints and variables, and multiple PCB platforms (form factors). Industry standards should be leveraged by domain. For example, LEF/DEF for the IC data and Excel or AIF for the package substrate data. This provides the engineers with the ability to visualize the complete system.

The most flexibility in the optimization flow exists in the package pin-out. However, not every pin on a package should be handled equally. Differential pairs need to be kept together, signal to power ratios must be considered and so forth. Therefore, a rule engine should be available to control/guide the pin optimization algorithms. Simply optimizing interconnect from pin to pin is no longer adequate. Optimization of pin-outs must consider any escape and breakout routing performed by the package substrate designer, as well as the board layout designer.

Many considerations and challenges must be overcome when considering a true cross-domain co-design platform to support future design requirements. I’ve briefly described several of capabilities that should be considered when attempting to develop a formal flow to meet these challenges:

• Optimization with escape and breakout routing
• Assembly and visualization of complete system
• Multi-mode connectivity management
• Rules based pin optimization
• Streamlined and automated library development
• Support for multiple designs/platforms

For a more complete discussion of this clear direction for the future of chip-package-board co-design, you can download a white paper here.

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