Chiplets and the Early Adopter’s Dilemma

Early adopters of a new technology often face a serious dilemma. On one hand, moving early means exploiting the most aggressive new technology available. But on the other hand, making early technology decisions can lock a product line into a path that will later become uncompetitive—either a single-vendor solution that can’t guarantee continuity of supply, or a roadmap that can’t shift and diversify with emerging market opportunities.

We are seeing this today in the chiplet arena. System designers are rushing to investigate chiplet-based design to move beyond the limitations and costs of huge single-die implementations. The most widely discussed chiplet designs depend upon silicon interposers—or their close relatives, embedded silicon bridges—as a substrate for mounting and interconnecting the multiple dies. In many ways, chiplets and silicon interposers appear to be a natural combination.

Fabricating the interdie connections on a silicon substrate allows much tighter bump spacing and line spacing, meaning more possible connections per millimeter of die edge, and hence greater interdie bandwidth per millimeter of die edge. This is a critical metric when partitioning a high-speed design across multiple dies. And for a given interconnect electronics, silicon offers a higher data rate than conventional organic substrates. Since early chiplet-based designs have been for high-end, high-priced assemblies such as datacenter CPUs and GPUs, where density and performance are non-negotiable but price is secondary, discussions of chiplets have come to virtually assume the use of silicon substrates. As one vendor recently said, “without interposers there can be no chiplets.”

But silicon interposers have some concerning characteristics as well.

Is there an alternative? To find it, we have to look not at the substrate technology, but on the dies themselves—at the tiny electronic circuits that drive the interconnect lines.

Read more here.

Fig.1: Eliyan’s NuLink PHY on standard packaging enables products with more ASICs and more memories than would be possible on advanced packaging.