Optimizing CD variation and defect reduction comprehensively, to improve results of a wide defect process window with a narrow CD distribution.
This study focused on the defect behavior analysis with CD variation on EUV via hole pattern using photolithographic process and etch transfer performance. While defect requirements are not as stringent for memory devices, logic devices must be defect-free. Currently, a defect which comes from the process or material can only be detected by top-down inspection approach, however, it is difficult to detect killer defect types such as incompletely opened holes. To develop 5- nm logic node, a hole pattern 15 nm or smaller is required. Identification of failure at the bottom of the hole becomes more challenging. Nevertheless, the process window margin by the amount of dose/focus is not fully explored to find the defect occurrence tendency. So far, there are reported analyses on the scaling of pattern and pitches. In this paper, we examine the process margin quantified by not only by exposure latitude and depth of focus, but also the comprehensive defect –free process window. In our previous study, the behavior of missing-hole type defects was examined and robust defect suppression result was introduced by utilizing a newly developed etching recipe. In this study, we optimized CD variation and defect reduction comprehensively, to introduce successful improvement results of a wide defect process window with a narrow CD distribution.
Authors: Takahiro Shiozawa, Arisa Hara, and Satoru Shimura of Tokyo Electron Kyushu Ltd. (Japan). Hidetami Yaegashi of Tokyo Electron Ltd. (Japan).
Click here to continue reading on SPIE’s website. Article available for members or for fee for non-members. The paper/poster session is part of the proceedings of the 2020 SPIE Advanced Lithography Conference, February 23-27, 2020 in San Jose, CA.
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