Correlation Study of Actual Temperature Profile and In-line Metrology Measurements for Within-Wafer Uniformity Improvement and Wafer Edge Yield Enhancement

Authors: Fang Fang (a), Alok Vaid (a), Alina Vinslava (a), Richard Casselberry (a), Shailendra Mishra (a), Dhairya Dixit (a), Padraig Timoney (a), Dinh Chu (b), Candice Porter (b), Da Song (b), Zhou Ren (b)
Key: (a) GLOBALFOUNDRIES, 400 Stone Break Extension, Malta, NY 12020; (b) KLA-Tencor Corporation, One Technology Drive, Milpitas, CA 95035

ABSTRACT
With advances in new technology it is getting more important to monitor all aspects of the influencing parameters in critical etch steps and utilize them as tuning knobs for within-wafer uniformity improvement and wafer edge yield enhancement. With this in mind, a study to dive into “measuring what matters” was designed to acquire electrostatic chuck (ESC) temperature measurements in actual process conditions using a KLA-Tencor SensArray EtchTemp-SE (ETSE) wafer.¹ The ESC temperature profile was measured on a 300mm wafer under plasma-on conditions to reproduce actual temperature conditions of wafers in the production process. Temperature maps were compared with a control reference (ESC temperature in static plasma-off status), and using this information, chamber to chamber matching was also investigated. Furthermore, a correlation study between ESC temperature and inline optical metrology measurements offers clear direction for process tuning through set-temperature modulations.

Key Words: SensArray EtchTemp-SE technology, electrostatic chuck (ESC) temperature, chamber to chamber mismatching, edge yield enhancement, recess depth, critical dimensions (CD)

1. INTRODUCTION

As semiconductor nodes advance and feature sizes shrink, every process knob becomes more important to fully characterize, understand and correlate to yield. Monitoring temperature in process critical etch steps and utilizing it to improve within wafer uniformity and edge yield issues is necessary for any high volume manufacturing facility. Temperature wafers (Figure 1) can measure on-wafer temperatures in full process conditions. This type of usage allows for monitoring and matching of not only tool hardware but process conditions affected by temperature. These wafers were used at GLOBALFOUNDRIES Fab 8 facilities to both test responsiveness of electrostatic chuck (ESC) temperature set point changes and correlations to CD and recess depth sizes in a process critical etch step in the fabrication process.

At GLOBALFOUNDRIES Fab 8, investigations into temperature on the 14nm FEOL critical etch process were carried out using the temperature wafer, because this process has a direct impact on yield. Specifically, we designed and conducted three items of investigation. First, ETSE wafer response at mid-outer and outer zone to ESC temperature set points was tested by modulating wafer temperature across four process modules. Second, chamber matching of temperature among four chambers at the critical point in an etch step with plasma on was studied. Third, correlation between wafer temperature and critical process parameters including recess depth and CD was studied in a detailed wafer-zonal level. The investigation results show that the temperature monitoring by ETSE wafer enables use of ESC zonal temperature control as good tuning knobs for within-wafer uniformity improvement and wafer edge yield enhancement.

Figure 1. Illustration of a SensArray EtchTemp-SE wafer and its working mechanism.

2. EXPERIMENTS WITH ETSE WAFER

2.1 ETSE wafer response to ESC temperature set points
To test responsiveness of ESC set points and on wafer temperature responsiveness to those set points, the temperature wafer was run at four different set points on two different process modules (referred to as PM1 and PM2). Temperature was decreased in 1°C steps for PM1 and increased in 1°C steps in PM2. Temperature maps were generated using KLA-Tencor SensArray wafers and mean temperature was analyzed for the outer and mid outer zones to match with the outer ring, or edge of a production wafer. The test results (Figure 2) show that ETSE wafer responds well to ESC temperature set points at mid outer zone and outer zone respectively: correlation R² = 0.9979 for outer ring PM1, 0.9981 for mid-outer ring PM1, 0.9979 outer ring PM2 and 0.9986 for mid-outer ring PM2.

Figure 2. ESC Chuck DOE to modulate wafer edge temperature: wafer temperature responding well with the ESC set point. Correlation R² = 0.9979 for outer ring PM1, 0.9981 for mid-outer ring PM1, 0.9979 outer ring PM2 and 0.9986 for mid-outer ring PM2.

Figure 3 shows the responses from the temperature change on the chuck. On-wafer temperatures differ from the chuck set point consistently by ~+1.5°C in the outer ring of the wafer and by >1.0°C in the mid outer ring; this is due to differences in the plasma at the edge of the wafer, which increase the temperature. Wafer maps provide a visual representation of how the on-wafer temperature changes when heaters on the chuck are adjusted. The linear regressions demonstrate the strong, direct correlation between the adjustments and the on-wafer temperature, and the ability for the tool hardware to compensate for differences in chamber matching temperatures.

This test demonstrates that the ETSE wafer is a reliable tool in temperature measurements for the following two studies: chamber temperature matching and correlation between temperature and CD.

Figure 3. ETSE wafer thermal maps responding to chuck temperature change on the outer ring of the wafer.

2.2 Chamber temperature matching
To test the chamber temperature matching on one etch tool, temperature traces were collected from the four chambers PM2, PM3, PM4 and PM5 during the plasma-on etch process. Wafer maps of the four chambers were calculated and plotted for chamber matching study.

Results for initial temperature data collection on four different PMs can be seen in Figure 4. These maps show the on-wafer temperature for the four different PMs under plasma-on conditions. From the figure, we can see that PM2 and PM3 show good matching to each other while PM4 is colder than baseline and PM5 runs hotter. Using this information, the temperature in PM4 was stepped up in four 1°C degree steps and measured at each step and the temperature in PM5 was stepped down in four 1°C steps and measured at each step. Both wafer mean temperature and temperature in the outer zones can be seen on the wafer maps generated from SensArray wafers.

This test displays the ETSE wafer ability of evaluating chamber temperature matching.

Figure 4. Plasma-on ETSE thermal maps from four etch process tool chambers. While PM2 and PM3 show good matching, PM4 and 5 showed mismatching. PM4 is colder and PM5 is hotter than the baseline.

2.3 Correlation between temperature and critical dimensions
To correlate CD and recess depth measurements to temperature, a PM of interest was monitored for temperature shortly before production wafers were processed through the same PM. CD and recess depth measurements were then taken from OCD (optical critical dimension) metrology tools. Raw data with X and Y coordinates were compared, and CD and recess depth sites within the same temperature zone controlled by tool hardware were used for analysis. Temperature versus CD or recess depth was plotted by zones determined by the ESC control, and linear regression analysis was conducted accordingly.

In wafer-zonal level, correlation was broken down into four zones: Inner, Mid Inner, Mid Outer and Outer – these zones can be seen in Figure 5. The correlation was done this way because of the ability to change the chuck temperature within these zones. The ESC has the capability to set temperatures in these zones independently and therefore data was analyzed to be able to turn the temperature knob on each individual zone. The results for CD correlation can be seen in Figure 6. The best correlation can be seen in the Outer and Inner zones with R² values of 0.7 and 0.81 respectively. The reverse correlation shows that as the wafer gets hotter the CD size gets smaller, potentially blowing out the feature and causing yield problems down the line. With this information, it becomes possible to use the outer chuck temperature knob to control the chuck temperature and therefore affect the CD in the manufacturing process.

Figure 5. Zones used for Correlation of CD and recess depth. These zones correspond with temperature knobs within the etch process tool hardware.

Figure 6. Zonal Analysis — 4-zone temperature correlation to CD. Strongest correlation is seen at the Mid Outer zone (R²= 0.8312), Inner Zone (R²= 0.8103) and Outer Zone (R²=0.6871)

In wafer-zonal level, results for correlation to recess depth can be seen in Figure 7. Correlation was broken down into the same four zones as CD correlation for the same reasons. Strong, direct correlation can be seen in the Outer, Mid Inner and Inner zones with R² values of 0.89, 0.83 and 0.69 respectively. The direct correlation implies that as the process temperature increases the depth of the recess also increases. This information is of critical importance for controlling temperature in the process module and introduces a knob for controlling the recess depth of the etch into silicon. By controlling the temperature on the outer zone of the wafer the recess depth can be tuned to the fab’s needs. With the results of the temperature modulation from the first experiment we can be confident that the temperature is at the correct setting for optimal processing for highest yield. in high volume manufacturing.

Figure 7. Zonal Analysis — 4-zone temperature correlation to recess depth. Strongest correlation is seen at the Outer Zone (R²= 0.8912), Mid Inner Zone (R²= 0.8329) and Inner Zone (R²=0.6904)

3. CONCLUSIONS

The investigation into the relationship between ESC zonal temperature and a critical etch process using KLA-Tencor’s EtchTemp-SE wafer shows that a temperature wafer is a reliable tool in temperature measurements and monitoring. The temperature wafer is capable of evaluating the quality of chamber temperature mismatching and providing guidance for etch tool chamber temperature tuning. Most critically, the temperature wafer enables use of ESC zonal temperature control as an important knob in controlling CD and recess depth during the etch process.

4. REFERENCES

[1] J. Newby, G. Bieli, M. Wollenweber; R. Melzer, T. Nogatz, J. Sobe, “Correlation Study of Spatial ESC Temperature Profile and Optical CD/SEM measurements to investigate silicon recess and gate CD after Etch,” Proc. of ASMC 2014, 25^th Annual pp. 136-138, 2014.

Originally published in SPIE Advanced Lithography. Fang Fang et al, “Correlation study of actual temperature profile and in-line metrology measurements for within-wafer uniformity improvement and wafer edge yield enhancement,” Proc. SPIE 10585, Metrology, Inspection, and Process Control for Microlithography XXXII, 105851Q (21 March 2018); doi: 10.1117/12.2297213