Cost Reduction, Power Management Get More Intense In IoT

Mass market strategies will affect requirements for what’s designed and how quickly.


Power has become a consideration even if there is a plug in the wall. But for applications sitting out who knows where in the (IoT), it is more than a consideration. It is one of the primary requirements, given the small size of these devices, rivaled only by cost.

Reflecting on what brought the industry to this point, Aveek Sarkar, vice president of product engineering and support at Ansys-Apache, pointed to the smartphone revolution that occurred between about 2008 and 2012. “We moved from clock speed of the laptop (i.e., the Intel/AMD wars), to the feature set on the mobile phone (between Apple and Samsung and HTC),” he observed. “Nobody really cared about the price because the carriers were subsidizing it. It was cool to have the next iPhone. Everybody would pay hand over fist for that, and that was driving smartphone activity.”

Since then more developed markets have started reaching saturation, and systems companies are looking to new buyers in India, China, and less-developed economies to sell their products. This has given rise to the low-end smartphone, such as those based on Google’s Android One.

A similar mass-market push can be seen in the automotive space, where an estimated 50% of a car’s cost is based on electronics. The amount of cabling put in a Land Rover, for example, costs about $3,000, Sarkar said. “Then, there is the whole IoT thing running our lives. If you believe even a fraction of it, it will be pretty cool, but all of that will require a vast amount of electronics, which has to be extremely low cost. When we look at all of these, the trend is going to be how we leverage all that we’ve achieved in the past several years in terms of power reduction, in terms of functionality, in terms of some of the technology nodes.”

“The electronics industry has to capitalize on this trend,” he said. “The design process will again go through a transformation because it’s no longer about just the feature or the clock speed. It’s going to be about how fast can you get it done because the IoT market is going to be like the app world. Once you standardize on the communication protocol in the IoT environment, everybody in China, India, United States, or anywhere in the world will jump in to give you the next smart sensor that can do a lot of things. So, how fast you can get to that market is going to become very key.”

It’s not just about how fast you get to market, though. It’s how fast and cheaply you can do it. To this end, accelerating the whole design process is going to be a major focus area for everybody, he predicts. “When we say accelerating the design process, we break it down into different sections like how to accelerate your sign-off process, from something that takes you 10 hours to run, we have to make it faster so it gets done in two or three hours, so you can converge quickly. How can we move up the information that you get from simulation — be it power simulation, be it timing, DRC, LVS, whatever — up in the design chain so you start getting that visibility sooner and earlier so that the whole design process gets compressed.”

The good news is that much of this work has been under way at the leading edge process nodes. Rolling it back to more established nodes is relatively straightforward.

Convergence and optimization
Mary Ann White, director of the product marketing for the Galaxy Design Platform at Synopsys, pointed out that synthesis is no longer just straight logic synthesis. It now has physical awareness built in to allow the engineering team to do design placement during synthesis and be able to look at congestion during synthesis. “It has so much back end know-how that you no longer have to do that first round of place and route to see up front what’s going on with your design. It’s been an evolutionary thing over the past several years, so there’s always something new coming from the place and route world into the synthesis without distracting from place and route, and what ends up happening is because you have more back-end knowledge up front, you don’t have to worry about the iteration at the back end, which tends to be time-consuming.”

While this isn’t just restricted to power, it does result in cost savings in the end, she said.

Further, more and more people want to do fast synthesis to get that what-if and determine what’s going on in terms of the overall area and budget without having to do the full place and route and timing analysis at the very end, White observed. “There is also a lot of prototyping occurring at the system level, so you have to have a lot of awareness, know what you are budgeting, and whether or not your design will meet that stringent budget up front. You don’t have to go all the way to the back end. Building more and more of that knowledge of what happens at the end of the line toward the front is something that we’ve done over the previous years.”

In this vein, AtrentaCTO Bernard Murphy pointed out that power, performance and area must be optimized together for IoT devices and that the power hierarchy constrains the physical hierarchy. “Each power or voltage domain requires separate power rails and switches, and it becomes very inefficient to have domains with otherwise identical power/voltage properties scattered around the layout. It is much more efficient in area (and quite possibly better also in power integrity) to combine these wherever possible. But that requires restructuring logic hierarchy at RTL to match the power hierarchy because changes in these hierarchies require changes in level shifters and isolation insertion, and also may require re-verification.”

Further, IoT devices have to be very, very inexpensive, which means they must be floor-planned as much as possible for connection by abutment (also potentially improving timing closure), he said. “That also requires restructuring, often partitioning bus fabric into components grouped in different physical units.”

In addition, subsystems (e.g., an ARM core or cores with cache memory and bus interfaces) have to be optimized and pre-hardened to squeeze out maximum performance, Murphy explained, but noted that this process is somewhat custom per usage because optimum pinout expectations differ from design to design. “This in turn requires a highly automated flow—otherwise it just takes too long per subsystem instance—to optimize. In some cases that means changing inferred logic to instantiated logic, technology mapping, which is replacing generic memories with technology-mapped memories, instantiating internal controls such as power management and test—MBIST and scan—and finally floor-planning for optimum performance and area before hardening.”

Cost savings in the IoT
One big cost savings is staying on more established manufacturing process nodes, White noted. “A lot of these IoT devices will be on the more established nodes like 55nm and above, and very few of them will go to 28nm. Even though 28nm will last a long time, it will take a while for many of these devices to get there. There is a plethora of power saving techniques for established nodes that are well defined that people could put in place. Especially at more established nodes, all the techniques to save power are definitely very established. More recently implemented techniques can be leveraged at older nodes, and there will likely be even more developed for new markets.”

When it comes down to it, everybody is sensitive to cost. “Whether it’s fabrication or manufacturing cost or design efficiency cost. In the end, if you have power efficiency built in from the beginning, to us that means design efficiency/silicon efficiency,” she added.

Steve Carlson, group director of marketing at Cadence, pointed to a complex market evolution in the IoT. “One thing that seems to be clear is that there are going to be a lot of design starts generated by the Samsungs and Apples — the biggest in the world — as well as garage-shop folks working off of Arduino platforms and things like that. When you talk about cost, the tradeoff between the design cost and the manufacturing cost is in there. If you go to an Arduino-based platform and write a little software, your design costs can be pretty darn low, but your per-unit price is going to be at a disadvantageous point, as is your form factor and the power characteristics of the device, particularly if you’re trying to do a battery-operated thing.”

He said there will be a natural miniaturization progression path “where we see there literally being tens of thousands of design starts that folks will start at the PCB level and then they may go into some custom packaging solutions. That’s a really interesting area as wel, where there’s of course the at the high end and silicon interposers, but also package in package, package on package and hundreds of variations. If you include the custom ones as well, there are literally thousands. Then you can still go smaller and still more energy efficient by integrating it into a single IC form factor. So we see this order of magnitude hierarchy of tens of thousands of PCB designs, thousands of SiP-based designs, and at least hundreds of monolithic IC kinds of designs. Each step in that miniaturization process gives you cost and form factor and power advantages. Those are really important in markets like IoT for wearables and medical and all the subcategories. At the chip level there’s this architectural tradeoff such that you’re trying to determine what’s the right processor for the job, and this is where the Tensilica cores come into play where they have a customizable instruction set so you can knock out unneeded instructions and add custom instructions.”

Tying power to cost
While it might not seem obvious at first glance, power ties into the issue of cost, Sarkar said. “Power is pretty much the fundamental thing behind all of the trends. For example, let’s say you have an IoT device that you designed to run at 200MHz but for some reason you messed up your timing closure and it came out to be 180 to 160MHz. That’s no big deal. You wouldn’t even notice if you were the consumer. But on the other hand, you didn’t do a good job in the power closure. You were supposed to design this thing to operate at 10 microwatts but you ended up using 45 microwatts. Just because you didn’t meet your power budget, this thing is going to be off. But, in the case of say, a spacecraft landing on a comet that can’t get power because it turned away from the sun, how much more poignant can it get? If you cannot operate the device because you did not do a good job on the power management, essentially it is going to be a dud.”

He said power handoff is becoming the key metric for winning business. “Even though we tend to be obsessed with the performance wars and the clock wars, overall, it is going to be power and heat and thermal that’s going to decide how these devices operate, even in the car,” he concluded.


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