CPF 2.0 Voltage Regulator And Analog Ports

By Luke Lang
CPF 2.0 was released more than a year and half ago, yet the majority of the designs are still done with CPF 1.1. This is one of those good news/bad news situations. The good news is that CPF 1.1 is perfectly adequate for majority of the LP designs. The bad news is that designers may not be aware of the new CPF 2.0 features that could be quite useful. This month, we will take a look at two new CPF 2.0 features – voltage regulator and analog port.

Voltage regulators are typically modeled as macro models in CPF 1.1. This has worked well for the implementation folks. But there is one problem for the verification folks. There is no support for automatic shutoff of the regulated domain when the reference voltage is shut off.

CPF 2.0 has added direct voltage regulator support in a very simple and straightforward manner. The simplest way to describe it is that a voltage regulator is modeled as a power switch, except the input (reference voltage) and output (regulated voltage) can have different voltages. The reference voltage is the base domain of the regulated voltage. When the base domain is shut off, the derived domain is also shut off. Some voltage regulators can shut off the regulated voltage by a control signal while the reference voltage is still on. This control signal is modeled as the shutoff condition of the reference voltage.

To model a power switch inside a macro model, the CPF coding looks like:

create_power_domain –name PD_switched –shutoff_condition En –base_domains PD_aon

For a voltage regulator, the CPF 2.0 coding looks like:

create_power_domain –name PD_vreg –shutoff_condition En –base_domains PD_aon
–power_source

The –power_source keyword specifies that PD_vreg and PD_aon can have different voltage.

Another new feature provides additional verification capability for analog IP and ports. IP blocks have always been represented by CPF macro model. If any of the IP interface pins are analog in nature, they must not be subject to the isolation and level shifting rules of the digital interface pins. This includes both verification and insertion of isolation and level shifter cells. In CPF 1.1, these analog interface pins are modeled as floating ports, rather than boundary ports of power domains. This means don’t touch and don’t verify.

Some designs have lots of analog IP’s. It is difficult to verify that these analog interface pins are connected correctly. Full-chip simulation may not catch incorrect connections because the analog behavioral models may not model these analog interface pins accurately enough to detect incorrect connection. As a result, CPF 2.0 has added the analog ports feature for macro models. Each analog port can have an optional user attribute string. When specified, Conformal Low Power (CLP) will verify that the driving and receiving analog ports have the same user attribute string. This provides an extra level of verification that was not available for floating ports

—Luke Lang is engineering director at Cadence.