Cracking The Mixed-Signal Verification Code

Rapid digitization in IoT, automotive, industrial, and communication industry segments are fueling semiconductor industry growth. This growth follows the “More than Moore” paradigm, where new design starts are spread across mature to advanced manufacturing nodes based on end-application targets. With this digitalization, data has become the most valuable resource.

Mixed-signal designs play a vital role in this semiconductor growth, serving as the link between the virtual and physical world. 80% of today’s design starts are mixed-signal bringing increased design complexity, shorter time-to-market cycles, and an increasing need for efficient verification coverage.

Modern day mixed-signal verification challenges
Outdated verification methodology: Legacy verification solutions assume that analog and digital portions of the design can be verified separately. However, increased interaction between the analog and digital domains within today’s mixed-signal ICs makes this “divide and conquer” verification approach inadequate. Analog and digital domains need to be simulated in tandem, with appropriate design abstractions based on the verification scope.

Need for speed/performance: Today’s IC designs are essentially multiple systems on a chip (SoC). For example, an ADAS system contains LIDAR, Radar, imagers, and sensors that interact with next-generation silicon architectures designed to select, condition, process, and analyze data. Complex subsystems increase functional verification coverage and performance verification requirements across multiple PVTs. Faster mixed-signal verification performance is absolutely essential to meet these verification requirements in a timely manner.

Complex use model: Traditional mixed-signal solutions were designed based on requirements set forth over 20 years ago. However, a concurrent analog and digital verification approach requires a team with diverse technical expertise to understand, setup, and efficiently debug mixed-signal verification. Figure 1 shows a typical mixed-signal verification team that includes an analog block designer, digital block designer, modeling engineer, and a top-level system integrator/verification expert. This team demands a verification solution with a simple use model and they should be able to reuse existing digital design verification infrastructure as is.

Figure 1: A typical mixed-signal verification team profile.

Mixed-signal debug: In mixed-signal design, errors most often occur at the interfaces between analog and digital blocks. Frequently, bugs in the interfaces are identifiable only at a higher level of hierarchy, sometimes at the I/O pins (Figure 2).

Figure 2: A common mixed-signal debug scenario.

Mixed-signal debug gets even more complicated when the design employs advanced, low-power techniques. For example, data corruption in a digital block due to faulty power sequencing can pass to an analog block, resulting in erroneous voltage conversion. Scenarios like this are difficult to debug by analog designers who are unaware of digital low-power techniques.

Introducing Symphony Mixed-Signal Platform
Symphony Mixed-Signal Platform (Figure 3) provides designers with unprecedented flexibility for choosing their own design methodology: bottom-up, top-down, or any combination of the two. Designers can make intelligent tradeoffs by choosing detailed, continuous analog models or SPICE for high accuracy, and discrete behavioral models for simulation performance.

Figure 3: Symphony Mixed-Signal Platform.

Accuracy and speed: Symphony’s modular architecture leverages Mentor’s Analog FastSPICE (AFS) circuit simulator to provide fast mixed-signal simulation performance with nanometer SPICE accuracy and capacity of 20M SPICE elements. With certified accuracy by the world’s leading foundries, AFS delivers 5–10x faster performance than traditional SPICE and 2–6x faster performance than parallel SPICE simulators. Symphony has been proven on a wide range of ICs and IC subsystems including ADCs, transceivers, PMICs, CMOS image sensors, multi-GHz PLLs/DLLs, and high-speed SerDes (Figure 4).

Figure 4: Symphony performance.

Design-aware architecture: What makes traditional, mixed-signal verification so complex is that these solutions rely on overly-complex simulator architectures for a “One-Size-Fits-All approach” even for the simplest mixed-signal designs. This approach adds unnecessary performance overhead, requires complex setup, and makes it very difficult for designers to analyze and debug verification results. New proprietary design-aware optimization algorithms automatically adapt to any design topology and provide optimal performance for mixed-signal design verification (Figure 5).

Figure 5: Comparing the traditional architecture to the Symphony design-aware architecture.

Mixed-signal debug capabilities: Debug capabilities should focus on areas where designers spend the most time debugging their designs. Symphony’s interactive Tcl mode allows designers to interact dynamically with a running simulation to effectively debug their designs. The Symphony Boundary Element (BE) browser allows designers to graphically visualize analog and digital portions of a design. The browser allows for a searchable representation of boundary elements and mixed-signal nets that can be cross-referenced across multiple visualization tools including a source browser, waveform viewer (EZwave) and schematic windows (Figure 6). This unified information presentation helps reduce debug time and improve overall productivity.

Figure 6: Symphony’s advanced debug capabilities.

Best-in-class usability: Symphony delivers an intuitive use model with a simple configuration file format and command structure that allows full reuse of existing digital/analog solver command line arguments (Figure 7).

Figure 7: Symphony’s simple command structure.

It is also integrated into leading schematic capture environments and works with both digital- and analog-centric flows. It offers extensive analog/digital boundary element support covering all signal types and multiple power domains, including those with dynamic supplies.

Conclusion
Verification of mixed-signal IP and SoCs is challenging. Mentor’s Symphony Mixed-Signal Platform is built on a design-aware architecture. It delivers accurate & fast mixed-signal simulation performance, powerful debugging capabilities, and best-in-class usability to solve modern day, mixed-signal verification challenges.

To learn more, download our new whitepaper: Simplifying Mixed-Signal Verification with the Symphony Platform